Tektronix Webcam 070-8030-01 User Manual
Theory of Operation
1780R-Series Service Manual
3–41
The oscillator output is divided by 4 with a Johnson counter internal to U990.
The counter has four outputs that are 90
The counter has four outputs that are 90
_ apart. These four signals drive a 4:1
multiplexer, also internal to U990, which is controlled by a flip-flop, U985 on
Diagram 14, through pins 8 and 9. By controlling the multiplexer the F
Diagram 14, through pins 8 and 9. By controlling the multiplexer the F
SC
signal
output on pin 16 of U990 can be phase shifted in 90
_ increments.
In NTSC, there are 227.5 cycles of F
SC
per horizontal line. Thus when the F
SC
signal is sampled each line, the samples will differ by 180
_ from one line to the
next. However phase shifting the F
SC
signal by 180
_ from line to line provides
successive samples that will be in phase. The counter and multiplexer in U990
provide the line rate phase shifting. In PAL a similar phase shift operation
occurs, except that the shift is 90
provide the line rate phase shifting. In PAL a similar phase shift operation
occurs, except that the shift is 90
_ per line.
The phase-shifted F
SC
(F
SC
feedback), output by U990, is latched (U995) and
fed to a Phase Detector, U1287. U1287 and Q1293 form a Charge-Pump Phase
Detector. The Phase Detector is gated on with a sample pulse from U1490A. The
sample pulse begins with the trigger from the 50% Sync Detector and ends from
140 to 280 ns later when the F
Detector. The Phase Detector is gated on with a sample pulse from U1490A. The
sample pulse begins with the trigger from the 50% Sync Detector and ends from
140 to 280 ns later when the F
SC
feedback signal transitions positive. During the
time the Phase Detector is gated on, current flows in and out of integrating
capacitors C1287 and C1291. The direction of the current flow is controlled by
the F
capacitors C1287 and C1291. The direction of the current flow is controlled by
the F
SC
feedback signal driving U1287D pin 2. When pin 2 is low, 2 mA of
current from the current source (U1287C) flows out of the integrating capacitors
through the collector of U1287D (pin 5). When pin 2 is high, the current from
U1287 is routed into a current mirror (Q1293) where it is multiplied by 3 and
then added to the integrating capacitors. An equilibrium condition exists when
the net charge transfer is zero; therefore, pin 2 will be low 3 times as long as it is
high when the loop is locked. R1185 and the integrating capacitors, C1287 and
C1291, form the loop filter that controls the phase-lock loop response. The net
current flow into the loop filter produces the VCO control voltage, which
controls the varactor (CR1288) through R1290.
through the collector of U1287D (pin 5). When pin 2 is high, the current from
U1287 is routed into a current mirror (Q1293) where it is multiplied by 3 and
then added to the integrating capacitors. An equilibrium condition exists when
the net charge transfer is zero; therefore, pin 2 will be low 3 times as long as it is
high when the loop is locked. R1185 and the integrating capacitors, C1287 and
C1291, form the loop filter that controls the phase-lock loop response. The net
current flow into the loop filter produces the VCO control voltage, which
controls the varactor (CR1288) through R1290.
In order to provide a fine phase adjustment for the Sync Locked Oscillator,
U1397 provides a separate discharge path for the loop filter capacitors (C1287
and C1291). When the Sample Gate goes low, U1287B turns off and U1287A
turns on. At the same time U1497B pin 8 goes low, turning on U1397D for one
subcarrier cycle. This allows the current source (U1287C) to discharge the loop
filter while U1397D is on. The amount of current flowing is dependent on the
setting of the Fine SCH Adjust, R1281. When R1281 is adjusted to have its
wiper near ground little or no current flows through this path; however, when the
wiper is near the other end of the control, up to 2 mA of current flows from the
loop filter capacitors back to the –12 volt supply. When charge is taken off the
loop filter capacitors the duty factor on the charge pump will change; pin 2 will
be high longer to restore the no net charge transfer condition. This retards the
oscillator phase relative to the Sample Gate. Range of the Fine SCH Adjust is
approximately 110
U1397 provides a separate discharge path for the loop filter capacitors (C1287
and C1291). When the Sample Gate goes low, U1287B turns off and U1287A
turns on. At the same time U1497B pin 8 goes low, turning on U1397D for one
subcarrier cycle. This allows the current source (U1287C) to discharge the loop
filter while U1397D is on. The amount of current flowing is dependent on the
setting of the Fine SCH Adjust, R1281. When R1281 is adjusted to have its
wiper near ground little or no current flows through this path; however, when the
wiper is near the other end of the control, up to 2 mA of current flows from the
loop filter capacitors back to the –12 volt supply. When charge is taken off the
loop filter capacitors the duty factor on the charge pump will change; pin 2 will
be high longer to restore the no net charge transfer condition. This retards the
oscillator phase relative to the Sample Gate. Range of the Fine SCH Adjust is
approximately 110
_.