Tektronix Webcam 070-8030-01 User Manual
Theory of Operation
1780R-Series Service Manual
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J595. Pins 7 and 8 of U495 go to connector J495. This connector is used by the
factory to connect to peripheral equipment when developing software.
factory to connect to peripheral equipment when developing software.
A to D Converter. The A/D Converter, U217, combines a 16-bit analog multiplex-
er with an 8-bit A/D Converter. The multiplexer is set by accessing the ADMUX
address region to activate the /ADMUX strobe. The least significant 4 bits of the
address (IA0..IA3) are used to set the multiplexer to 1 of 16 values. Using the
address lines instead of the data lines provides adequate setup and hold times.
Once the multiplexer is set, it requires 2.5
er with an 8-bit A/D Converter. The multiplexer is set by accessing the ADMUX
address region to activate the /ADMUX strobe. The least significant 4 bits of the
address (IA0..IA3) are used to set the multiplexer to 1 of 16 values. Using the
address lines instead of the data lines provides adequate setup and hold times.
Once the multiplexer is set, it requires 2.5
ms for the output to stabilize on the
MUX OUT line. MUX OUT is low-pass filtered (R315 and C315) to remove
high frequency noise and then input to the converter COMP IN.
high frequency noise and then input to the converter COMP IN.
The converter is started by the MPU writing to the ADCS address, which
activates the /ADCS chip select. U120C ANDs /ADCS with /WR and inverts the
result to produce an active high START pulse. 10
activates the /ADCS chip select. U120C ANDs /ADCS with /WR and inverts the
result to produce an active high START pulse. 10
ms after the START pulse, the
End Of Convert (EOC) line goes low and stays low until the conversion is
completed. When the conversion is complete, EOC returns to high. EOC can be
read by the Master MPU as one of the miscellaneous input bits.
completed. When the conversion is complete, EOC returns to high. EOC can be
read by the Master MPU as one of the miscellaneous input bits.
I/O. In order to provide an external ground closure interface, miscellaneous input
bits are connected to one of two multiplexers, U190 and U390, which allows for
a maximum of 16 input bits from J199, S385, or U217. When the bits are read,
the Master MPU does a read to the MISC address region, which activates the
/MISCS chip select. For reads, U130 (a PAL) qualifies this with /RD to produce
the active low /MRDCS. When /MRDCS is low, the multiplexers place their data
on the Internal Data (ID) Bus. The least significant address bit (IA0) is used to
select the A or B side of the multiplexers.
bits are connected to one of two multiplexers, U190 and U390, which allows for
a maximum of 16 input bits from J199, S385, or U217. When the bits are read,
the Master MPU does a read to the MISC address region, which activates the
/MISCS chip select. For reads, U130 (a PAL) qualifies this with /RD to produce
the active low /MRDCS. When /MRDCS is low, the multiplexers place their data
on the Internal Data (ID) Bus. The least significant address bit (IA0) is used to
select the A or B side of the multiplexers.
S385 controls three of the B inputs to U390, allowing ID1, ID2, and ID3 to be
set for specific functions when IA0 goes high to select the B inputs of U390.
set for specific functions when IA0 goes high to select the B inputs of U390.
Output bits, to control front-panel indicators, are set by writing to output register
U392. It is cleared at power-up by the Master MPU-generated /RSTO signal.
Bits are set in the register when the MPU writes to the MISC address region.
U130 qualifies the /MISCS signal with /WR to produce /MWRCS. The rising
edge of /MWRCS latches the least significant 6 bits of the data bus (ID0..ID5)
into the register.
U392. It is cleared at power-up by the Master MPU-generated /RSTO signal.
Bits are set in the register when the MPU writes to the MISC address region.
U130 qualifies the /MISCS signal with /WR to produce /MWRCS. The rising
edge of /MWRCS latches the least significant 6 bits of the data bus (ID0..ID5)
into the register.
The least significant output of U392 is connected through a dropping resistor,
R390, to the diagnostic LED, DS491. A low on this bit turns on the LED. Bits 1
and 2 are connected through R491 and R492 to front-panel LEDs R0 and R1. A
low on these bits turns on the LED. The upper three bits of the register are not
used.
R390, to the diagnostic LED, DS491. A low on this bit turns on the LED. Bits 1
and 2 are connected through R491 and R492 to front-panel LEDs R0 and R1. A
low on these bits turns on the LED. The upper three bits of the register are not
used.
Remote Sync. A 2 to 5 volt, 25 or 50 Hz (PAL) or 30 or 60 Hz (NTSC) square
wave input to Q391 will synchronize the Field Sweep Gate (Diagram 10) to
wave input to Q391 will synchronize the Field Sweep Gate (Diagram 10) to