Tektronix Webcam 070-8030-01 User Manual
Theory of Operation
3–88
1780R-Series Service Manual
up, the output of the Phase Detector falls below the trigger threshold of the
unijunction-wired Acquisition Sweep (Q411 and Q412), to turn off the ramp. If
the loop unlocks, the output of the Phase Detector (through the Error Amplifier)
goes above the Acquisition Sweep threshold and the ramp is again generated,
line by line, until lock re-occurs.
unijunction-wired Acquisition Sweep (Q411 and Q412), to turn off the ramp. If
the loop unlocks, the output of the Phase Detector (through the Error Amplifier)
goes above the Acquisition Sweep threshold and the ramp is again generated,
line by line, until lock re-occurs.
VCO and Frequency Divider. The active components of the VCO are high-speed
buffer inverters. Its output is approximately 8 MHz (512
buffer inverters. Its output is approximately 8 MHz (512
×
H rate). Frequency for
625/50 is a little higher than that for 525/60 operation, but both are within the
operating range of the VCO. Frequency control for the VCO is through Q309
and CR310, a Schottky diode, that duty cycle modulates C210 to vary the
frequency of the VCO. The VCO output, in addition to being the input to the
divide-by-512 array, is also buffered, filtered, and sent off the Oscillator circuit
board (through the Interconnect) to the Filter circuit board, see Diagram <35>.
operating range of the VCO. Frequency control for the VCO is through Q309
and CR310, a Schottky diode, that duty cycle modulates C210 to vary the
frequency of the VCO. The VCO output, in addition to being the input to the
divide-by-512 array, is also buffered, filtered, and sent off the Oscillator circuit
board (through the Interconnect) to the Filter circuit board, see Diagram <35>.
The VCO output clocks U403, a 20-input Programmable Logic Array. A
divide-by-2 output (4 MHz) is buffered, filtered, and sent off the Oscillator
circuit board (through the Interconnect) to the Filter circuit board as the Clock/2
signal. U403 performs an additional divide by 256 (for a total of 512) to generate
the AFC H rate sync. U214 is a serial-input, parallel-output register used to delay
the AFC sync for correct phase match with direct sync. The signal can be
delayed up to 8 Clock/2 cycles; however, 4 cycles provides optimum phase
match to eliminate a shift in sweep starting point when switching between Direct
and AFC Sync.
divide-by-2 output (4 MHz) is buffered, filtered, and sent off the Oscillator
circuit board (through the Interconnect) to the Filter circuit board as the Clock/2
signal. U403 performs an additional divide by 256 (for a total of 512) to generate
the AFC H rate sync. U214 is a serial-input, parallel-output register used to delay
the AFC sync for correct phase match with direct sync. The signal can be
delayed up to 8 Clock/2 cycles; however, 4 cycles provides optimum phase
match to eliminate a shift in sweep starting point when switching between Direct
and AFC Sync.
The divide-by-512 output from U403 is the AFC H rate sync signal to the Phase
Detector that completes the phase-locked loop.
Detector that completes the phase-locked loop.
Post Regulators. U135, U136, and U147 are solid state voltage regulators for the
Oscillator circuit board. They provide +12 V (U147), –12 V (U135), and +5 V
decoupled (U136) for the circuits on this board.
Oscillator circuit board. They provide +12 V (U147), –12 V (U135), and +5 V
decoupled (U136) for the circuits on this board.