Tektronix Webcam 070-8030-01 User Manual
Theory of Operation
1780R-Series Service Manual
3–99
Sample-and-Hold. During the time that the LC Oscillator is being checked against
the 10 MHz Reference, U406A is closed and U406B is open; during the time
that timing cursor information is being output, the switches are in the opposite
configuration. With C403 paralleling C404, and the loop filter disconnected,
C403 (after a few seconds) reaches the same voltage that C404 has in the
oscillator calibration mode. This makes the control voltage and the frequency the
same for both calibration and timing cursor output. L115 in the LC Oscillator
should be adjusted so that the Varactor drive voltage (TP100) is +8 volts, at
room temperature.
the 10 MHz Reference, U406A is closed and U406B is open; during the time
that timing cursor information is being output, the switches are in the opposite
configuration. With C403 paralleling C404, and the loop filter disconnected,
C403 (after a few seconds) reaches the same voltage that C404 has in the
oscillator calibration mode. This makes the control voltage and the frequency the
same for both calibration and timing cursor output. L115 in the LC Oscillator
should be adjusted so that the Varactor drive voltage (TP100) is +8 volts, at
room temperature.
Analog Delay. Q411 is normally off, and CR310 and CR311 are forward
conducting to allow U211 to hold (TP315) just a few millivolts from ground,
which gives the ramp a consistent 0-volt reference starting point. When the
Digital Counter reaches the end of its count, it triggers the one-shot, U218B, and
generates the Ramp Start signal. The Ramp Start signal turns on Q411 to back
bias CR310 and CR311. A constant current source, Q311, charges C313 in a
linear fashion, to generate a ramp signal. The ramp drives one input to a
comparator, U318, where it is compared to a DC voltage from the Microproces-
sor. The comparator outputs a TTL pulse, proportionally delayed in time by the
DC voltage level from the Microprocessor.
conducting to allow U211 to hold (TP315) just a few millivolts from ground,
which gives the ramp a consistent 0-volt reference starting point. When the
Digital Counter reaches the end of its count, it triggers the one-shot, U218B, and
generates the Ramp Start signal. The Ramp Start signal turns on Q411 to back
bias CR310 and CR311. A constant current source, Q311, charges C313 in a
linear fashion, to generate a ramp signal. The ramp drives one input to a
comparator, U318, where it is compared to a DC voltage from the Microproces-
sor. The comparator outputs a TTL pulse, proportionally delayed in time by the
DC voltage level from the Microprocessor.
The two cursors are output time shared at a 30 Hz rate. U406D and U406C are
switches that steer Cursor 1 and Cursor 2 voltages to the comparator, U318,
depending on which cursor is being driven.
switches that steer Cursor 1 and Cursor 2 voltages to the comparator, U318,
depending on which cursor is being driven.
The comparator (U318) output ANDs with a permanent low to trigger a pulse
shaping one-shot (U218A) that outputs a 1
shaping one-shot (U218A) that outputs a 1
ms pulse that drives the cursor shaper
driving the Waveform CRT cathode. The timing cursor locate mode uses the 1
ms
pulse to bright-up the display; the entire pulse width is used during locate, not
just the leading edge, to drive the Z-Axis Amplifier.
just the leading edge, to drive the Z-Axis Amplifier.
Cursor Versus Sweep Synchronization and Cursor Enable. The timing cursors
must be synchronous with the sweep signal. For instance, in a two-line sweep the
timing cursors must always start at the first displayed line, and not the second. A
TRIG EN signal originating from the sweep circuitry on Diagram 10 tells the
timing cursor circuitry of an impending sweep start. When TRIG EN is true, the
timing cursors can start counting on the leading edge of –REF H SYNC.
must be synchronous with the sweep signal. For instance, in a two-line sweep the
timing cursors must always start at the first displayed line, and not the second. A
TRIG EN signal originating from the sweep circuitry on Diagram 10 tells the
timing cursor circuitry of an impending sweep start. When TRIG EN is true, the
timing cursors can start counting on the leading edge of –REF H SYNC.
It is possible for the timing cursors to delay greater than two lines. Due to this,
timing cursors may be displayed only on every other sweep sequence of a
two-line sweep. U429A does this function by passing only half of the TRIG EN
pulses to the control IC, U426. The signal out of U429A is called HALF TRIG
EN. When TRIG EN and HALF TRIG EN are both true, and other control line
conditions are met, COUNTER ENABLE DATA becomes true.
timing cursors may be displayed only on every other sweep sequence of a
two-line sweep. U429A does this function by passing only half of the TRIG EN
pulses to the control IC, U426. The signal out of U429A is called HALF TRIG
EN. When TRIG EN and HALF TRIG EN are both true, and other control line
conditions are met, COUNTER ENABLE DATA becomes true.
The –REF H SYNC signal from U596 on Diagram 9 and the COUNTER
ENABLE DATA signal from the control IC U426 are both applied to U429B.
ENABLE DATA signal from the control IC U426 are both applied to U429B.