Tektronix Webcam 070-8030-01 User Manual
Theory of Operation
1780R-Series Service Manual
3–17
Diagram 7 Vertical Control Logic, Calibrator, & Cursors
The Microprocessor controls the vertical functions through three 8-bit latches.
These are all static logic levels. Dynamic switching, such as the Ch-A/Ch-B
Parade display, is achieved by state machines in logic arrays, and is timed by
sync from the Horizontal Timing circuit. Analog voltages, such as position and
gain, come from the Sample-and-Hold circuits on Schematic 12.
These are all static logic levels. Dynamic switching, such as the Ch-A/Ch-B
Parade display, is achieved by state machines in logic arrays, and is timed by
sync from the Horizontal Timing circuit. Analog voltages, such as position and
gain, come from the Sample-and-Hold circuits on Schematic 12.
Input Selection. Input selection data (encoded into 8 bits) is latched in from the
data bus by U1516. Selection of inputs to the Differential Amplifier occurs in
U1415, a logic array, and the two latches at its output. Bits I1 through I4 contain
the + Amplifier switch information, while bits I5 through I7 contain the
– Amplifier information. The PAR MODE bit provides additional information to
U1415 (I8) when Parade mode is selected. Table 3–2 shows the coding of the
inputs. The table also shows the signal that is currently being used as the internal
reference source.
data bus by U1516. Selection of inputs to the Differential Amplifier occurs in
U1415, a logic array, and the two latches at its output. Bits I1 through I4 contain
the + Amplifier switch information, while bits I5 through I7 contain the
– Amplifier information. The PAR MODE bit provides additional information to
U1415 (I8) when Parade mode is selected. Table 3–2 shows the coding of the
inputs. The table also shows the signal that is currently being used as the internal
reference source.
Overview
Circuit Theory