Tektronix DTG5000 Series User Manual

The jitter tolerance testing is performed in the follow-

ing broad steps:

1.

The skew in data is varied until the worst point is 

determined. This test is performed over several 

iterations as illustrated in Figure 3. The signal 

generator providing the TMDS is then set to 

produce this worst-case level of skew.

2.

Measuring Jitter Margins: several measurements 

involve injecting a specified amount of jitter to the 

clock signal path. Three measurements are 

performed over two test cases. Again, these 

Data and Clock components are injected only into 

the system clock path. The measurements and test 

cases are as follows:

– Data Jitter amplitude (D

jw

)

– Data Jitter Frequency at 500 KHz and 

Clock Jitter Frequency at 10 MHz 

– Data Jitter Frequency at 1 MHz and Clock Jitter 

Frequency at 7 MHz.

– Worst Data Jitter Amplitude

– Data Jitter Frequency at 500 KHz and Clock 

Jitter Frequency at 10 MHz 

– Data Jitter Frequency at 1 MHz and Clock 

Jitter Frequency at 7 MHz.

– Worst Clock Jitter Amplitude

– Data Jitter Frequency at 500 KHz and Clock 

Jitter Frequency at 10 MHz 

– Data Jitter Frequency at 1 MHz and Clock 

Jitter Frequency at 7 MHz.

Figure 4 explains the measurement criteria for 

D_JITTER and C_JITTER margins. The tests need to

be performed at all pixel clock rates supported by the

device under test. Because of the many parameters to

be adjusted and the tight margins, this test can be

rather complex and time-consuming. 

The minimum differential sensitivity test is common to

many serial standards. The test confirms that the Sink

meets interoperability requirements even when it

experiences attenuated differential voltage swings. 

A TMDS signal generator with the ability to change

amplitude is the proper tool for this test. The source 

is used to generate a Sink-supported 27 MHz video

format that repeats the RGB gray ramp signal from 

0 to 255 during each video period. The test starts at

170 mV V

DIFF

on all pairs, then the differential signal

amplitude is reduced in steps of 20 mV until the Sink

device reports an error. If the minimum V

DIFF

to which

the Sink responds without error is less than 150 mV,

the device passes the test. The test stops when 

minimum V

DIFF

reaches 70 mV. Another important 

element of this test is that it is performed at two 

different V

ICM

(common-mode voltage) settings, 

namely 3.0 V and 3.13 V. The DTG5000 Series offers 

a specific termination voltage capability that allows

the generation of the TMDS signals at the appropriate

levels without the requirement for external adapters

such as Bias Tees.

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