Oracle Vacuum Cleaner CPU-56T User Manual
Maps and Registers
Physical Memory Map
110
SPARC/CPU−56T
Physical Memory Map
The UltraSPARC−IIi+ has a 41−bit wide physical address range. This address range is
divided into some specified areas for e.g. the main memory or the PCI bus.
divided into some specified areas for e.g. the main memory or the PCI bus.
a
Each area is subdivided into other areas, e.g. the main memory area is subdivided into the
different memory module areas with the memory banks. Some areas are subdivided
further down to one register with one byte, i.e. the System Control registers in the EBus
area are byte−oriented.
different memory module areas with the memory banks. Some areas are subdivided
further down to one register with one byte, i.e. the System Control registers in the EBus
area are byte−oriented.
a
The tables on the following pages describe the areas with the related address maps. If an
address map is subdivided into other areas, a separate table is available below and a
reference to this table can be found in the description column.
address map is subdivided into other areas, a separate table is available below and a
reference to this table can be found in the description column.
UltraSPARC−IIi+ Physical Address Memory Map
The main address map gives an overview of the whole address space of the
UltraSPARC−IIi+ CPU. This address range is used for the main memory, and the PCI bus.
Each defined address space is divided into subspaces which are described in the next
sections.
UltraSPARC−IIi+ CPU. This address range is used for the main memory, and the PCI bus.
Each defined address space is divided into subspaces which are described in the next
sections.
Table 20:
UltraSPARC−IIi+ Main Address Map
Physical Address Range PA<40..0>
Size
Description
Access
000.0000.0000
16
− 001.FFFF.FFFF
16
8 GByte
Main memory
Cacheable
002.0000.0000
16
a
− 007.FFFF.FFFF
16
aa
Reserved
Cacheable
008.0000.0000
16
a
− 1FB.FFFF.FFFF
16
aa
Reserved
Noncacheable
1FC.0000.0000
16
a
− 1FD.FFFF.FFFF
16
8 GByte
Reserved, do not use
a
Noncacheable
1FE.0000.0000
16
a
− 1FF.FFFF.FFFF
16
8 GByte
a
PCI bus, processor
subsystem, memory,
clock control, and ECU
subsystem, memory,
clock control, and ECU
Noncacheable
Memory Address Map
The main memory address range is divided between on−board memory and the
MEM−550 memory modules. Two banks of 256 MByte and four banks of 256 MByte result
in a total amount of up to 2 GB main memory.
MEM−550 memory modules. Two banks of 256 MByte and four banks of 256 MByte result
in a total amount of up to 2 GB main memory.
Table 21:
Main Memory Address Map
Physical Address Range PA<41..0>
Size
Bank
Memory Location
DIMM Type
000.0000.0000
16
a
− 000.0FFF.FFFF
16
256 MByte
0
On−board memory
DIMM 0
000.8000.0000
16
a
− 000.8FFF.FFFF
16
256 MByte
2
aa
DIMM 1