Oracle Vacuum Cleaner CPU-56T User Manual
Physical Memory Map
Maps and Registers
SPARC/CPU−56T
113
Address Range in PA<40:0>
Description
EBus CS#
Size
1FF.F010.0000
16
a
− 1FF.F0FF.FFFF
16
15 MByte
0
User flash memory on the EBus (if
SW1−1 is ON or if bit 0 of the
Miscellaneous Control register is
set to 1)
SW1−1 is ON or if bit 0 of the
Miscellaneous Control register is
set to 1)
1FF.F100.6000
16
a
− 1FF.F100.7FFF
16
8 KByte
1
RTC/NVRAM on the EBus
1FF.F110.0000
16
a
− 1FF.F11F.FFFF
16
1 MByte
2
PLCC PROM mirror area
(independent of SW2−1 and bit 0
of the Miscellaneous Control
register)
(independent of SW2−1 and bit 0
of the Miscellaneous Control
register)
1FF.F130.0100
16
a
− 1FF.F130.0108
16
8 Byte
4
Serial controller on the EBus Serial
interface A
interface A
1FF.F130.0200
16
a
− 1FF.F130.0208
16
8 Byte
4
Serial controller on the EBus
a
Serial interface B
1FF.F130.0300
16
a
− 1FF.F130.0308
16
8 Byte
4
Serial controller on the EBus
Serial interface C
Serial interface C
1FF.F130.0400
16
a
− 1FF.F130.0408
16
8 Byte
4
Serial controller on the EBus
Serial interface D
Serial interface D
1FF.F160.0100
16
a
− 1FF.F160.01FF
16
256 Byte
7
System Configuration register on
the EBus
the EBus
1FF.F170.0000
16
a
− 1FF.F17F.FFFF
16
1 MByte
n.a.
PCIO configuration registers