Oracle Vacuum Cleaner CPU-56T User Manual
System Configuration Registers
Maps and Registers
SPARC/CPU−56T
123
Watchdog Timer Status Register
The Watchdog Timer Status register reflects the watchdog timer status.
Address: 1FF.F160.0134
16
Table 34:
Watchdog Timer Status Register
Bit
Name
Description
Default
Access
0
STAT WDOG
This bit reflects the status of the watchdog timer.
a
0: The watchdog timer has not reached the interrupt
time.
time.
a
1: The watchdog timer has exceeded the interrupt
time. It is necessary to trigger the watchdog timer.
time. It is necessary to trigger the watchdog timer.
0
2
r
7..1
0
Reserved
0000000
2
r
Timer Registers
The timer can be used as two independent 16−bit countdown timers with a timer interval
of 10
of 10
µs and a total maximum run−out time of 655.35 ms. Two independent interrupts are
possible, which can be enabled or disabled (refer to Interrupt Registers" section). A
counter read−back register set is also available which always shows the correct timer
value.
counter read−back register set is also available which always shows the correct timer
value.
Both timers can also be used as one 32−bit countdown timer with a timer interval of 10
µs
and a total run−out time of 42949.67295 s or 11h, 55min, 49 s and 672.95 ms. In this mode
only one interrupt is available and possible.
only one interrupt is available and possible.
a
The timer counts down from its initial value to zero in intervals of 10
µs. The initial value
can be set by software from 1 to 65535 in the 16−bit mode or to 4294967295 in the 32−bit
mode, which results in a timer period of 10
mode, which results in a timer period of 10
µs to 655.35 ms in 16−bit mode or 42949.67295
s in 32−bit mode. If the timer has reached zero, an interrupt is generated, if enabled, and
the timer loads his initial value to count down again.
the timer loads his initial value to count down again.
a
The timer has eleven registers in total. The first register is used to control the timer mode,
one register is used to clear timer overruns, one register is used to read the timer overrun
status, four registers are used for setting the initial timer values and the last four registers
are used to read the current value of the countdown timers.
one register is used to clear timer overruns, one register is used to read the timer overrun
status, four registers are used for setting the initial timer values and the last four registers
are used to read the current value of the countdown timers.
a
Timer Control Register
This register is used to set up the timer. If the timer is set to zero, the timer is off and no
interrupts are generated. However, the Timer Status register will not be cleared. The
normal timer tolerance is 100 ppm. During the first countdown after the timer activation,
however, the timer tolerance is increased to 10
interrupts are generated. However, the Timer Status register will not be cleared. The
normal timer tolerance is 100 ppm. During the first countdown after the timer activation,
however, the timer tolerance is increased to 10
µs.