Oracle Vacuum Cleaner CPU-56T User Manual
Maps and Registers
System Configuration Registers
134
SPARC/CPU−56T
Address: 1FF.F160.01EF
16
Table 47:
Hardware Revision Register
Bit
Name
Description
Access
7..0
HW REVISION
Status of the Board
00
00
16
: PCB revision: 1.0 and FPGA revision: 0
16
01
16
: PCB revision: 1.0 and FPGA revision: 1
16
02
16
: PCB revision: 1.0 and FPGA revision: 2
16
10
16
: PCB revision: 1.1 and FPGA revision: 10
16
11
16
: PCB revision: 1.1 and FPGA revision: 11
16
12
16
: PCB revision 1.2 and FPGA revision 12
16
13
16
a
− FE
16
: Reserved
FF
16
: No valid hardware revision
r
I2C Registers
The I
2
C registers implemented in the FPGA are used to access the local I
2
C bus for the
SPD, BIBs and temperature sensors.
Address: 1FF.F160.01FE
16
Table 48:
I2C 1 Register
Bit
Name
Description
a
Default
Access
0
I2C−DATAIN1
This register bit reflects the current status of the
I
I
2
C−1 data line.
0: I
2
C−1 dataline is 0.
1: I
2
C−1 dataline is 1.
−
r
1
I2C−CLK1
This bit corresponds to the I
2
C clock line and must
be set by software to toggle the I2C clock.
0: I
0: I
2
C−1 clock is 0.
1: I
2
C−1 clock is 1.
−
w
2
I2C−DATAOUT1
This bit is used by software to write to the I
2
C
dataline.
a
0: The I
2
C−1 dataline is driven low.
1: The I
2
C−1 dataline is driven high by an external
pull−up.
1
2
r/w
7..3
−
Reserved
00000
2
r/w
aa