MiTAC 8170 User Manual
117
8170 N/B MAINTENANCE
5.1 Pentium 4(Willamette/Northwood) mFC-PGA2 478 pin
Name Type
Description
V
CCIOPLL
Input
V
CCIOPLL
provides isolated power for internal processor system
bus PLLs. Follow he guidelines for V
CCA
, and refer to the Intel®
Pentium® 4 Processor in the 478-pin Package and Intel® 850
Chipset Platform Design Guide for complete implementation
details.
Chipset Platform Design Guide for complete implementation
details.
V
CCSENSE
Output
V
CCSENSE
is an isolated low impedance connection to processor
core power(V
CC
). It can be used to sense or measure power near
the silicon with little noise.
VCCVID
Input
There is no imput voltage requirement for VCCVID for designs
intended tosupport only the Pentium 4 processor in the 478-pin
package. Refer to the Intel® Pentium® 4 Processor in the
478-pin Package and Intel® 850 Chipset Platform Design
Guide for more information.
intended tosupport only the Pentium 4 processor in the 478-pin
package. Refer to the Intel® Pentium® 4 Processor in the
478-pin Package and Intel® 850 Chipset Platform Design
Guide for more information.
VID[4:0]
Output
VID[4:0] (Voltage ID) pins can be used to support automatic
selection of power supply voltages (Vcc). These pins are not
signals, but are either an open circuit or a short circuit to VSS
on the processor. The combination of opens and shorts
defines the voltage required by the processor. The VID pins are
needed to cleanly support processor voltage specification
variations. See
selection of power supply voltages (Vcc). These pins are not
signals, but are either an open circuit or a short circuit to VSS
on the processor. The combination of opens and shorts
defines the voltage required by the processor. The VID pins are
needed to cleanly support processor voltage specification
variations. See
1.4
for definitions of these pins. The power
supply must supply the voltage that is requested by these pins,
or disable itself.
or disable itself.
V
SSA
Input V
SSA
is the isolated ground for internal PLLs.
V
SSSENSE
Output
V
SSSENSE
is an isolated low impedance connection to processor
core V
SS
. It can be used to sense or measure ground near the
silicon with little noise
TMS
Input
TMS (Test Mode Select) is a JTAG specification support signal
used by debug tools.
used by debug tools.
TRDY#
Input
TRDY# (Target Ready) is asserted by the target to indicate that
it is ready to receive a write or implicit writeback data transfer.
TRDY# must connect the appropriate pins of all system bus
agents.
it is ready to receive a write or implicit writeback data transfer.
TRDY# must connect the appropriate pins of all system bus
agents.
TRST#
Input
TRST# (Test Reset) resets the Test Access Port (TAP) logic.
TRST# must be driven low during power on Reset. This can be
done with a 680 . pull-down resistor.
TRST# must be driven low during power on Reset. This can be
done with a 680 . pull-down resistor.
VCCA
Input
VCCA provides isolated power for the internal processor core
PLLs. Refer to the Intel® Pentium® 4 Processor in the 478-pin
Package and Intel® 850 Chipset Platform Design Guide for
complete implementation details.
PLLs. Refer to the Intel® Pentium® 4 Processor in the 478-pin
Package and Intel® 850 Chipset Platform Design Guide for
complete implementation details.