MiTAC 8170 User Manual
129
8170 N/B MAINTENANCE
5.3 Intel 82801BA(I/O Controller HUB )
System Management Interface Signals
Name Type
Description
INTRUDER#
I
Intruder Detect: This signal can be set to disable system if box
detected open. This signal’s status is readable, so it can be used like a
GPI if the Intruder Detection is not needed.
detected open. This signal’s status is readable, so it can be used like a
GPI if the Intruder Detection is not needed.
SMLINK[1:0]
I/OD System Management Link: These signals are an SMBus link to an
optional external system management ASIC or LAN controller.
External pull-ups are required.
External pull-ups are required.
Note:
that SMLINK[0] corresponds to an SMBus Clock signal and
SMLINK[1] corresponds to an SMBus Data signal.
SMLINK[1] corresponds to an SMBus Data signal.
Real Time Clock Interface
Name Type
Description
RTCX1
Special
Crystal Input 1: This signal is connected to the 32.768 KHz crystal.
If no external crystal is used, then RTCX1 can be driven with the
desired clock rate.
If no external crystal is used, then RTCX1 can be driven with the
desired clock rate.
RTCX2
Special
Crystal Input 2: This signal is connected to the 32.768 KHz crystal.
If no external crystal is used, then RTCX2 should be left floating.
If no external crystal is used, then RTCX2 should be left floating.
Other Clocks
Name Type
Description
CLK14
I
Oscillator Clock: CLK14 is used for 8254 timers and runs at
14.31818 MHz.
82801BA ICH2: This clock is permitted to stop during S3 (or lower)
states.
82801BAM ICH2-M: This clock is permitted to stop during S1 (or
lower) states.
14.31818 MHz.
82801BA ICH2: This clock is permitted to stop during S3 (or lower)
states.
82801BAM ICH2-M: This clock is permitted to stop during S1 (or
lower) states.
CLK48
I
48 MHz Clock: CLK48 is used to for the USB controller and runs at
48 MHz.
82801BA ICH2: This clock is permitted to stop during S3 (or lower)
states.
82801BAM ICH2-M: This clock is permitted to stop during S1 (or
lower) states.
48 MHz.
82801BA ICH2: This clock is permitted to stop during S3 (or lower)
states.
82801BAM ICH2-M: This clock is permitted to stop during S1 (or
lower) states.
CLK66
I
66 MHz Clock: CLK66 is used to for the hub interface and runs at 66
MHz.
82801BA ICH2: This clock is permitted to stop during S3 (or lower)
states.
82801BAM ICH2-M: This clock is permitted to stop during S1 (or
lower) states.
MHz.
82801BA ICH2: This clock is permitted to stop during S3 (or lower)
states.
82801BAM ICH2-M: This clock is permitted to stop during S1 (or
lower) states.
Miscellaneous Signals
Name Type
Description
SPKR
O
Speaker: The SPKR signal is the output of counter 2 and is internally
"ANDed" with Port 61h bit 1 to provide Speaker Data Enable. This
signal drives an external speaker driver device, which in turn drives
the system speaker. Upon PCIRST#, its output state is 1.
"ANDed" with Port 61h bit 1 to provide Speaker Data Enable. This
signal drives an external speaker driver device, which in turn drives
the system speaker. Upon PCIRST#, its output state is 1.
Note:
SPKR is sampled at the rising edge of PWROK as a functional strap.
RTCRST#
I
RTC Reset: When asserted, this signal resets register bits in the RTC
well and sets the RTC_PWR_STS bit (bit 2 in GEN_PMCON3
register).
well and sets the RTC_PWR_STS bit (bit 2 in GEN_PMCON3
register).
Note:
Clearing CMOS in an ICH2-based platform can be done by using a
jumper on RTCRST# or GPI, or using SAFEMODE strap.
Implementations should not attempt to clear CMOS by using a
jumper to pull VccRTC low.
jumper on RTCRST# or GPI, or using SAFEMODE strap.
Implementations should not attempt to clear CMOS by using a
jumper to pull VccRTC low.
TP0
(ICH2 0nly)
(ICH2 0nly)
I
Test Point (82801BA ICH2): This signal must have an external
pull-up to VccSus3_3.
pull-up to VccSus3_3.
FS0
I
Functional Strap: This signal is reserved for future use. There is an
internal pullup resistor on this signal.
internal pullup resistor on this signal.
AC’97 Link Signals
Name Type
Description
AC_RST#
O
AC97 Reset: Master H/W reset to external Codec(s)
AC_SYNC
O
AC97 Sync: 48 KHz fixed rate sample sync to the Codec(s)
AC_BIT_CLK
I
AC97 Bit Clock: 12.288 MHz serial data clock generated by the
external Codec(s). See Note.
external Codec(s). See Note.
AC_SDOUT
O
AC97 Serial Data Out: Serial TDM data output to the Codec(s)
Note:
AC_SDOUT is sampled at the rising edge of PWROK as a functional
strap..
strap..
AC_SDIN[1:0]
I
AC97 Serial Data In 0: Serial TDM data inputs from the Codecs.
See Note.
See Note.