LSI 53C810A User Manual
3-14
PCI Functional Description
RTA
Received Target Abort (from Master)
12
A master device should set this bit whenever its
transaction is terminated with a target abort. All master
devices should implement this bit.
transaction is terminated with a target abort. All master
devices should implement this bit.
R
Reserved
11
DT[1:0]
DEVSEL/ Timing
[10:9]
These bits encode the timing of DEVSEL/.
These bits are read only and should indicate the slowest
time that a device asserts DEVSEL/ for any bus
command except Configuration Read and Configuration
Write. The LSI53C810A supports 0b01.
time that a device asserts DEVSEL/ for any bus
command except Configuration Read and Configuration
Write. The LSI53C810A supports 0b01.
DPR
Data Parity Reported
8
This bit is set when the following three conditions are
met:
met:
•
The bus agent asserted PERR/ itself or observed
PERR/ asserted.
PERR/ asserted.
•
The agent setting this bit acted as the bus master for
the operation in which the error occurred.
the operation in which the error occurred.
•
The Parity Error Response bit in the Command
register is set.
register is set.
R
Reserved
[7:0]
0b00
Fast
0b01
Medium
0b10
Slow
0b11
Reserved