Lantronix DSTni-EX User Manual
49
Endpoint Control Registers
The Endpoint Control registers contain the endpoint control bits for the 16 endpoints available
on USB for a decoded address. These four bits define all the control necessary for any one
endpoint. Endpoint 0 (ENDPT0) is associated with control pipe 0, which is required by USB for
all functions. Therefore, after receiving a USB_RST interrupt, the microprocessor sets ENDPT0
to contain 0Dh.
on USB for a decoded address. These four bits define all the control necessary for any one
endpoint. Endpoint 0 (ENDPT0) is associated with control pipe 0, which is required by USB for
all functions. Therefore, after receiving a USB_RST interrupt, the microprocessor sets ENDPT0
to contain 0Dh.
Table 4-21. Endpoint Control Registers
BIT
7
6
5
4
3
2
1
0
OFFSET
11h through 7h
FIELDS
HOST_WO_HUB
RETRY_DIS
///
EP_CTL_DIS
EP_RX_EN
EP_TX_EN
EP_STALL
EP_HSHK
RESET
0
0
0
0
0 0 0
0
RW
R/W
R/W
R/W
R/W
R/W R/W R/W
R/W
Table 4-22. Endpoint Control Register Definitions
Bits
Field Name
Description
7 HOST_WO_HUB
Host-Mode-Only Bit
A host-mode-only bit that is present only in the Control register for endpoint 0
(endpt0_rg).
1 = host can communicate to a directly connected low-speed device.
0 = host produces the PRE_PID, then switches to low-speed signaling to send a
token to a low-speed device. This is required to communicate with a low-speed
device through a hub.
A host-mode-only bit that is present only in the Control register for endpoint 0
(endpt0_rg).
1 = host can communicate to a directly connected low-speed device.
0 = host produces the PRE_PID, then switches to low-speed signaling to send a
token to a low-speed device. This is required to communicate with a low-speed
device through a hub.
6
RETRY_DIS
Host-Mode-Only Bit
A host-mode-only bit that is present only in the control register for endpoint 0
(endpt0_rg).
1 = prevent host retrying NAK’ed transactions. When a transaction is NAK'ed, the
NAK PID updates the BDT PID field and the token-done interrupt is set.
(Required setting when host tries to poll an interrupt endpoint.)
0 = NAK'ed transactions are retried in hardware.
A host-mode-only bit that is present only in the control register for endpoint 0
(endpt0_rg).
1 = prevent host retrying NAK’ed transactions. When a transaction is NAK'ed, the
NAK PID updates the BDT PID field and the token-done interrupt is set.
(Required setting when host tries to poll an interrupt endpoint.)
0 = NAK'ed transactions are retried in hardware.
5 ///
Reserved
4
EP_CTL_ DIS
3
EP_RX_EN
2
EP_TX_EN
Endpoint Enable
Defines whether an endpoint is enabled and the direction of the endpoint. Table
4-23 shows the enable/direction control values.
Defines whether an endpoint is enabled and the direction of the endpoint. Table
4-23 shows the enable/direction control values.
1
EP_STALL
Endpoint Stalled
This bit has priority over all control bits in the Endpoint Enable register; however,
it is only valid if EP_IN_EN=1 or EP_OUT_EN=1. Any access to this endpoint
causes the USB to return a STALL handshake. After an endpoint stalls, it requires
intervention from the host controller.
This bit has priority over all control bits in the Endpoint Enable register; however,
it is only valid if EP_IN_EN=1 or EP_OUT_EN=1. Any access to this endpoint
causes the USB to return a STALL handshake. After an endpoint stalls, it requires
intervention from the host controller.
0
EP_HSHK
Endpoint Handshaking
1 = defines whether the endpoint performs handshaking during a transaction to
this endpoint
This bit is generally set, unless it is an isochronous endpoint.
1 = defines whether the endpoint performs handshaking during a transaction to
this endpoint
This bit is generally set, unless it is an isochronous endpoint.