Apollo ESP6000 User Manual
ECM-3612
66 ECM-3612 User’s Manual
3.5.3
Advanced Chipset Features
This section allows you to configure the system based on the specific features of the
installed chipset. This chipset manages bus speeds and access to system memory
resources, such as DRAM and the external cache. It also coordinates communications
between the conventional ISA bus and the PCI bus. It must be stated that these items
should never need to be altered. The default settings have been chosen because they
provide the best operating conditions for your system. The only time you might consider
making any changes would be if you discovered that data was being lost while using your
system.
The first chipset settings deal with CPU access to dynamic random access memory
(DRAM). The default timings have been carefully chosen and should only be altered if data
is being lost. Such a scenario might well occur if your system had mixed speed DRAM
chips installed so that greater delays may be required to preserve the integrity of the data
held in the slower memory chips.
installed chipset. This chipset manages bus speeds and access to system memory
resources, such as DRAM and the external cache. It also coordinates communications
between the conventional ISA bus and the PCI bus. It must be stated that these items
should never need to be altered. The default settings have been chosen because they
provide the best operating conditions for your system. The only time you might consider
making any changes would be if you discovered that data was being lost while using your
system.
The first chipset settings deal with CPU access to dynamic random access memory
(DRAM). The default timings have been carefully chosen and should only be altered if data
is being lost. Such a scenario might well occur if your system had mixed speed DRAM
chips installed so that greater delays may be required to preserve the integrity of the data
held in the slower memory chips.
3.5.3.1 DRAM
Clock
Set the memory bus frequency to operate at various values for the proper memory clock
setting.
The choices: Host CLK, HCLK-33M, HCLK+33M.
setting.
The choices: Host CLK, HCLK-33M, HCLK+33M.
3.5.3.2 SDRAM Cycle Length
When synchronous DRAM is installed, the number of clock cycles of CAS latency depends
on the DRAM timing. Do not reset this field from the default value specified by the system
designer.
When synchronous DRAM is installed, the number of clock cycles of CAS latency depends
on the DRAM timing. Do not reset this field from the default value specified by the system
designer.
The choices: 3, 2.