IBM Intel Xeon E5502 46M1077 User Manual
Product codes
46M1077
Intel® Xeon® Processor 5500 Series Datasheet, Volume 2
61
Register Description
2.7.7
SAD_INTERLEAVE_LIST_0
SAD_INTERLEAVE_LIST_1
SAD_INTERLEAVE_LIST_2
SAD_INTERLEAVE_LIST_3
SAD_INTERLEAVE_LIST_4
SAD_INTERLEAVE_LIST_5
SAD_INTERLEAVE_LIST_6
SAD_INTERLEAVE_LIST_7
SAD DRAM package assignments. When the corresponding DRAM_RULE hits, a 3-bit
number (determined by mode) is used to index into the interleave_list to determine
which package is the HOME for this address.
number (determined by mode) is used to index into the interleave_list to determine
which package is the HOME for this address.
00: IOH
01: Socket 0
10: Socket 1
11: Reserved
01: Socket 0
10: Socket 1
11: Reserved
2.8
Intel QPI Link Registers
2.8.1
QPI_QPILCP_L0
QPI_QPILCP_L1
Intel QPI Link Capability. Function 4 in the below table applies only to processors with
two Intel QPI links.
two Intel QPI links.
;
Device:
0
Function: 1
Offset:
C0h, C4h, C8h, CCh, D0h, D4h, D8h, DCh
Access as a Dword
Bit
Type
Reset
Value
Description
29:28
RW
-
PACKAGE7. Package for index value 7 of interleaves.
25:24
RW
-
PACKAGE6. Package for index value 6 of interleaves.
21:20
RW
-
PACKAGE5. Package for index value 5 of interleaves.
17:16
RW
-
PACKAGE4. Package for index value 4 of interleaves.
13:12
RW
-
PACKAGE3. Package for index value 3 of interleaves.
9:8
RW
-
PACKAGE2. Package for index value 2 of interleaves.
5:4
RW
-
PACKAGE1. Package for index value 1 of interleaves.
1:0
RW
-
PACKAGE0. Package for index value 0 of interleaves.
Device:
2
Function: 0, 4
Offset:
40h
Access as a Dword
Bit
Type
Reset
Value
Description
27:26
RO
-
VN0_CRDTS_DATA. VN0 Credits per Data MC
00 - 0 credits
01 - 1
10 - 2 to 8
11 - RSVD
00 - 0 credits
01 - 1
10 - 2 to 8
11 - RSVD