IBM Intel Xeon E5502 46M1077 User Manual
Product codes
46M1077
Intel® Xeon® Processor 5500 Series Datasheet, Volume 2
79
Register Description
2.11.10 MC_SCRUBADDR_LO
This register contains part of the address of the last patrol scrub request issued. When
running Memtest, the failing address is logged in this register on Memtest errors.
Software can write the next address to be scrubbed into this register. Patrol scrubs
must be disabled to reliably write this register.
running Memtest, the failing address is logged in this register on Memtest errors.
Software can write the next address to be scrubbed into this register. Patrol scrubs
must be disabled to reliably write this register.
2.11.11 MC_SCRUBADDR_HI
This register pair contains part of the address of the last patrol scrub request issued.
When running memtest, the failing address is logged in this register on memtest
errors. Software can write the next address into this register. Scrubbing must be
disabled to reliably read and write this register.
When running memtest, the failing address is logged in this register on memtest
errors. Software can write the next address into this register. Scrubbing must be
disabled to reliably read and write this register.
Device:
3
Function: 0
Offset:
78h
Access as a Dword
Bit
Type
Reset
Value
Description
29:14
RW
0
PAGE. Contains the row of the last scrub issued. Can be written to specify the
next scrub address with STARTSCRUB in the MC_SCRUB_CONTROL register.
13:0
RW
0
COLUMN. Contains the column of the last scrub issued. Can be written to
specify the next scrub address with STARTSCRUB in the MC_SCRUB_CONTROL
register.
Device:
3
Function: 0
Offset:
7Ch
Access as a Dword
Bit
Type
Reset
Value
Description
12
RO
0
MEMBIST_INPROGRESS. When this bit is asserted by hardware
MemTest/MemInit is in progress.
11
RO
0
MEMBIST_CMPLT. When this bit is asserted by hardware MemTest/MemInit is
complete.
10
WO
0
RESET_MEMBIST_STATUS. When this bit is written to a 1, the status field
MEMBIST_CMPLT is cleared.
9:8
RW
0
CHNL. Can be written to specify the next scrub address with STARTSCRUB in
the MC_SCRUB_CONTROL register. This register is not updated with channel
address of the last scrub address issued.
7:6
RW
0
DIMM. Contains the dimm of the last scrub issued. Can be written to specify
the next scrub address with STARTSCRUB in the MC_SCRUB_CONTROL register.
5:4
RW
0
RANK. Contains the rank of the last scrub issued. Can be written to specify the
next scrub address with STARTSCRUB in the MC_SCRUB_CONTROL register.
3:0
RW
0
BANK. Contains the bank of the last scrub issued. Can be written to specify the
next scrub address with STARTSCRUB in the MC_SCRUB_CONTROL register.