IBM Intel Xeon E5504 46M1078 User Manual
Product codes
46M1078
Register Description
112
Intel® Xeon® Processor 5500 Series Datasheet, Volume 2
2.16.4
MC_SAG_CH0_0
MC_SAG_CH0_1
MC_SAG_CH0_2
MC_SAG_CH0_3
MC_SAG_CH0_4
MC_SAG_CH0_5
MC_SAG_CH0_6
MC_SAG_CH0_7
MC_SAG_CH1_0
MC_SAG_CH1_1
MC_SAG_CH1_2
MC_SAG_CH1_3
MC_SAG_CH1_4
MC_SAG_CH1_5
MC_SAG_CH1_6
MC_SAG_CH1_7
MC_SAG_CH2_0
MC_SAG_CH2_1
MC_SAG_CH2_2
MC_SAG_CH2_3
MC_SAG_CH2_4
MC_SAG_CH2_5
MC_SAG_CH2_6
MC_SAG_CH2_7
Channel Segment Address Registers. For each of the 8 interleave ranges, they specify
the offset between the System Address and the Memory Address and the System
Address bits used for level 1 interleave, which should not be translated to Memory
Address bits. Memory Address is calculated from System Address and the contents of
these registers by the following algorithm:
the offset between the System Address and the Memory Address and the System
Address bits used for level 1 interleave, which should not be translated to Memory
Address bits. Memory Address is calculated from System Address and the contents of
these registers by the following algorithm:
m[39:16] = SystemAddress[39:16] + (sign extend {Offset[23:0]});
m[15:6] = SystemAddress[15:6];
If (Removed[2]) {bit 8 removed};
If (Removed[1]) {bit 7 removed};
If (Removed[0]) {bit 6 removed};
MemoryAddress[36:6] = m[36:6];
m[15:6] = SystemAddress[15:6];
If (Removed[2]) {bit 8 removed};
If (Removed[1]) {bit 7 removed};
If (Removed[0]) {bit 6 removed};
MemoryAddress[36:6] = m[36:6];
The table below summarizes the combinations of removed bits and divide-by-3
operations for the various supported interleave configurations. All other combinations
are not supported.
operations for the various supported interleave configurations. All other combinations
are not supported.
Note:
If any of bits [8:6] are removed, the higher order bits are shifted down.
Removed [8:6]
Divide-By-3
Interleave
000
0
None
001
0
2-Way
011
0
4-Way
000
1
3-Way
001
1
6-Way