IBM Intel Xeon E5504 46M1078 User Manual

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Intel® Xeon® Processor 5500 Series Datasheet, Volume 2

The processor contains 6 PCI devices within a single physical component. The 
configuration registers for these devices are mapped as devices residing on the PCI bus 
assigned for the processor socket. Bus number is derived by the max bus range setting 
and processor socket number.

• Device 0: Generic processor non-core. Device 0, Function 0 contains the generic 

non-core configuration registers for the processor and resides at DID (Device ID) of 
2C40h. Device 0, Function 1 contains the System Address Decode registers and 
resides at DID of 2C01h.

• Device 2: Intel QPI. Device 2, Function 0 contains the Intel® QuickPath 

Interconnect configuration registers for Intel QPI Link 0 and resides at DID of 
2C10h. Device 2, Function 1 contains the physical layer registers for Intel QPI Link 
0 and resides at DID of 2C11h. Device 2, Function 4 contains the Intel® QuickPath 
configuration registers for Intel® QuickPath Interconnect Link 1 and resides at DID 
of 2C14h. Device 2, Function 5 contains the physical layer registers for Intel QPI 
Link 1 and resides at DID of 2C15h. Functions 4 and 5 only apply to processors with 
two Intel QPI links.

• Device 3: Integrated Memory Controller. Device 3, Function 0 contains the general 

registers for the Integrated Memory Controller and resides at DID of 2C18h. Device 
3, Function 1 contains the Target Address Decode registers for the Integrated 
Memory Controller and resides at DID of 2C19h. Device 3, Function 2 contains the 
RAS registers for the Integrated Memory Controller and resides at DID of 2C1Ah. 
Device 3, Function 4 contains the test registers for the Integrated Memory 
Controller and resides at DID of 2C1Ch. Function 2 only applies to processors 
supporting registered DIMMs.

• Device 4: Integrated Memory Controller Channel 0. Device 4, Function 0 contains 

the control registers for Integrated Memory Controller Channel 0 and resides at 

RSVD

Reserved Bit. This bit is reserved for future expansion and must not be written. The PCI 

Local Bus Specification requires that reserved bits must be preserved. Any software that 

modifies a register that contains a reserved bit is responsible for reading the register, 

modifying the desired bits, and writing back the result.

Reserved Bits

Some of the processor registers described in this section contain reserved bits. These bits 

are labeled “Reserved”. Software must deal correctly with fields that are reserved. On 

reads, software must use appropriate masks to extract the defined bits and not rely on 

reserved bits being any particular value. On writes, software must ensure that the values 

of reserved bit positions are preserved. That is, the values of reserved bit positions must 

first be read, merged with the new values for other bit positions and then written back. 

Note that software does not need to perform a read-merge-write operation for the 

Configuration Address (CONFIG_ADDRESS) register.

Reserved 

Registers

In addition to reserved bits within a register, the processor contains address locations in 

the configuration space that are marked either “Reserved” or “Intel Reserved”. The 

processor responds to accesses to “Reserved” address locations by completing the host 

cycle. When a “Reserved” register location is read, a zero value is returned. (“Reserved” 

registers can be 8, 16, or 32 bits in size). Writes to “Reserved” registers have no effect on 

the processor. Registers that are marked as “Intel Reserved” must not be modified by 

system software. Writes to “Intel Reserved” registers may cause system failure. Reads to 

“Intel Reserved” registers may return a non-zero value.

Default Value 

upon a Reset

Upon a reset, the processor sets all of its internal configuration registers to predetermined 

default states. Some register values at reset are determined by external strapping 

options. The default state represents the minimum functionality feature set required to 

successfully bring up the system. Hence, it does not represent the optimal system 

configuration. It is the responsibility of the system initialization software (usually BIOS) to 

properly determine the DRAM configurations, operating parameters and optional system 

features that are applicable, and to program the processor registers accordingly.

“ST” appended to 

the end of a bit 

name

The bit is “sticky” or unchanged by a hard reset. These bits can only be cleared by a 

PWRGOOD reset.