IBM Intel Xeon E5504 46M1078 User Manual
Product codes
46M1078
Intel® Xeon® Processor 5500 Series Datasheet, Volume 2
47
Register Description
2.5.5
HDR - Header Type Register
This register identifies the header layout of the configuration space.
2.5.6
SID/SVID - Subsystem Identity/Subsystem Vendor
Identification Register
This register identifies the manufacturer of the system. This 32-bit register uniquely
identifies any PCI device.
identifies any PCI device.
Device:
0
Function:
0-1
Offset:
0Eh
Device:
2
Function:
0-1, 4-5
Offset:
0Eh
Device:
3
Function:
0-2, 4
Offset:
0Eh
Device:
4-6
Function:
0-3
Offset:
0Eh
Bit
Type
Reset
Value
Description
7
RO
1
Multi-function Device.
Selects whether this is a multi-function device, that may have alternative
Selects whether this is a multi-function device, that may have alternative
configuration layouts. This bit is hardwired to ‘1’ for devices in the processor.
6:0
RO
0
Configuration Layout.
This field identifies the format of the configuration header layout for a PCI-to-
This field identifies the format of the configuration header layout for a PCI-to-
PCI bridge from bytes 10h through 3Fh.
For all devices the default is 00h, indicating a conventional type 00h PCI header.
For all devices the default is 00h, indicating a conventional type 00h PCI header.
Device:
0
Function:
0-1
Offset:
2Ch, 2Eh
Device:
2
Function:
0-1, 4-5
Offset:
2Ch, 2Eh
Device:
3
Function:
0-2, 4
Offset:
2Ch, 2Eh
Device:
4-6
Function:
0-3
Offset:
2Ch, 2Eh
Access as a Dword
Bit
Type
Reset
Value
Description
31:16
RWO
8086h
Subsystem Identification Number:
The default value specifies Intel
15:0
RWO
8086h
Vendor Identification Number.
The default value specifies Intel.