IBM Intel Xeon E5504 46M1078 User Manual
Product codes
46M1078
Register Description
66
Intel® Xeon® Processor 5500 Series Datasheet, Volume 2
2.9
Intel QPI Physical Layer Registers
2.9.1
QPI_0_PH_CPR
QPI_1_PH_CPR
Intel QPI Physical Layer Capability Register.
18
RO
-
Agent_101_Router. Indicates agent 101 is a router agent.
17
RO
-
Agent_101_Firmware. Indicates agent 101 is a firmware agent.
16
RO
-
Agent_101_Config. Indicates agent 101 is a configuration agent.
15
RO
-
Agent_110_Caching. Indicates agent 110 is a caching agent.
14
RO
-
Agent_110_Home. Indicates agent 110 is a home agent.
13
RO
-
Agent_110_IO_Proxy. Indicates agent 110 is an IO Proxy agent.
12
RO
-
RSVD.
10
RO
-
Agent_110_Router. Indicates agent 110 is a router agent.
9
RO
-
Agent_110_Firmware. Indicates agent 110 is a firmware agent
8
RO
-
Agent_110_Config. Indicates agent 110 is a configuration agent.
7
RO
-
Agent_111_Caching. Indicates agent 111 is a caching agent.
6
RO
-
Agent_111_Home. Indicates agent 111 is a home agent.
5
RO
-
Agent_111_IO_Proxy. Indicates agent 111 is an IO Proxy agent.
4
RO
-
RSVD.
2
RO
-
Agent_111_Router. Indicates agent 111 is a router agent.
1
RO
-
Agent_111_Firmware. Indicates agent 111 is a firmware agent.
0
RO
-
Agent_111_Config. Indicates agent 111 is a configuration agent.
Device:
2
Function: 0, 4
Offset:
CCh
Access as a Dword
Bit
Type
Reset
Value
Description
Device:
2
Function: 1, 5
Offset:
68h
Access as a Dword
Bit
Type
Reset
Value
Description
29
RO
-
LFSR_POLYNOMIAL. Agent's ITU polynomial capability for loopback.
28:24
RO
-
NUMBER_OF_TX_LANES. Number of Tx lanes with which an implementation
can operate for full width.
Bit 28 - If set, 20 lanes.
The bit indicating the maximum lanes will determine the number of
control/status bits implemented in Tx/Rx Data lane Control/Status Registers.
23
RO
-
PRBS_CAPABILITY. If set, implementation is capable of using specified
pattern in bitlock/retraining.
22
RO
-
SCRAMBLE_CAPABILITY. If set, implementation is capable of data
scrambling/descrambling with LFSR.