IBM Intel Xeon E5504 46M1078 User Manual

92

Intel® Xeon® Processor 5500 Series Datasheet, Volume 2

DDR3 Configuration Command. This register is used to issue commands to the DIMMs 
such as MRS commands. The register is used by setting one of the *_VALID bits along 
with the appropriate address and destination RANK. The command is then issued 
directly to the DIMM. Care must be taken in using this register as there is no 
enforcement of timing parameters related to the action taken by a DDR3CMD write. 
This register has no effect after MC_CONTROL.INIT_DONE is set.

28

RW

0

PRECHARGE_VALID. Indicates current command is for a precharge 

command.

27

RW

0

ACTIVATE_VALID. Indicates current command is for an activate command.

26

RW

0

REG_VALID. Indicates current command is for a registered DIMM config write 

Bit is cleared by hardware on issuance. This bit applies only to processors 

supporting registered DIMMs.

25

RW

0

WR_VALID. Indicates current command is for a write CAS. Bit is cleared by 

hardware on issuance.

24

RW

0

RD_VALID. Indicates current command is for a read CAS. Bit is cleared by 

hardware on issuance.

23

RW

0

MRS_VALID. Indicates current command is an MRS command. Bit is cleared 

by hardware on issuance.

22:20

RW

0

RANK. Destination rank for command.

19:16

RW

0

MRS_BA. Address bits driven to DDR_BA[2:0] pins for the DRAM command 

being issued due to a valid bit being set in this register.

15:0

RW

0

MRS_ADDR. Address bits driven to DDR_MA pins for the DRAM command 

being issued due to a valid bit being set in this register.