IBM Intel Xeon E5506 46M1079 User Manual
Product codes
46M1079
Intel® Xeon® Processors 5500 Series Electrical Specifications
14
Intel
®
Xeon
®
Processor 5500 Series Datasheet, Volume 1
2.1.3
Platform Environmental Control Interface (PECI)
PECI is an Intel proprietary interface that provides a communication channel between
Intel processors and chipset components to external thermal monitoring devices. The
Intel Xeon Processor 5500 Series contains a Digital Thermal Sensor (DTS) that reports
a relative die temperature as an offset from Thermal Control Circuit (TCC) activation
temperature. Temperature sensors located throughout the die are implemented as
analog-to-digital converters calibrated at the factory. PECI provides an interface for
external devices to read processor temperature, perform processor manageability
functions, and manage processor interface tuning and diagnostics. Please refer to
Intel processors and chipset components to external thermal monitoring devices. The
Intel Xeon Processor 5500 Series contains a Digital Thermal Sensor (DTS) that reports
a relative die temperature as an offset from Thermal Control Circuit (TCC) activation
temperature. Temperature sensors located throughout the die are implemented as
analog-to-digital converters calibrated at the factory. PECI provides an interface for
external devices to read processor temperature, perform processor manageability
functions, and manage processor interface tuning and diagnostics. Please refer to
for processor specific implementation details for PECI.
The PECI interface operates at a nominal voltage set by V
TTD
. The set of DC electrical
is used with devices normally operating from a V
TTD
interface supply.
2.1.3.1
Input Device Hysteresis
The PECI client and host input buffers must use a Schmitt-triggered input design for
improved noise immunity. Please refer to
improved noise immunity. Please refer to
.
2.1.4
Processor Sideband Signals
Intel Xeon Processor 5500 Series include sideband signals that provide a variety of
functions. Details can be found in
functions. Details can be found in
and the applicable platform design guide.
All Asynchronous Processor Sideband signals are required to be asserted/deasserted
for at least eight BCLKs in order for the processor to recognize the proper signal state.
See
for at least eight BCLKs in order for the processor to recognize the proper signal state.
See
for DC specifications.
2.1.5
System Reference Clock
The processor core, processor uncore, Intel QuickPath Interconnect link, and DDR3
memory interface frequencies are generated from BCLK_DP and BCLK_DN signals.
There is no direct link between core frequency and Intel QuickPath Interconnect link
frequency (e.g., no core frequency to Intel QuickPath Interconnect multiplier). The
processor maximum core frequency, Intel QuickPath Interconnect link frequency and
memory interface frequencies are generated from BCLK_DP and BCLK_DN signals.
There is no direct link between core frequency and Intel QuickPath Interconnect link
frequency (e.g., no core frequency to Intel QuickPath Interconnect multiplier). The
processor maximum core frequency, Intel QuickPath Interconnect link frequency and
Figure 2-2. Input Device Hysteresis
Minimum V
P
Maximum V
P
Minimum V
N
Maximum V
N
PECI High Range
PECI Low Range
Valid Input
Signal Range
Signal Range
Minimum
Hysteresis
Hysteresis
V
TTD
PECI Ground