SUPER MICRO Computer IRV-3702 User Manual
2
S
ECTION
2 - S
YSTEM
D
ESCRIPTION
The following sections describe the major system features of the IRV-3702 All-In-One Single Board
Computer.
P
ROCESSOR
The IRV-3702 SBC supports the Intel Celeron processor up to 500MHz. The Celeron microprocessor
includes MMX media enhancement technology, dynamic execution technology, a 32Kbyte
(16Kbyte/16Kbyte) non-blocking, level-one cache that provides fast access to heavily used data, and
128Kbyte L2 cache. The on-board jumper selectable clock generator and ZIF CPU socket makes
upgrading to a higher performance CPU easy. Some of the distinctive features of the Celeron
processor include:
includes MMX media enhancement technology, dynamic execution technology, a 32Kbyte
(16Kbyte/16Kbyte) non-blocking, level-one cache that provides fast access to heavily used data, and
128Kbyte L2 cache. The on-board jumper selectable clock generator and ZIF CPU socket makes
upgrading to a higher performance CPU easy. Some of the distinctive features of the Celeron
processor include:
•
Enhanced 64-bit data bus
•
Integrated 128Kbyte L2 cache
•
16Kbyte code and 16Kbyte data caches
•
1G-byte Directly Addressable Memory Space
•
Dynamic execution technology
•
MMX multimedia technology
•
On-chip Pipelined Floating Point Processor
•
66 MHz multi-transaction system bus
•
Integrated Memory Manager
•
Branch prediction feature
S
YSTEM
M
EMORY
(SDRAM)
The IRV-3702 SBC can support up to 1G-bytes of synchronous dynamic random access memory
(SDRAM) organized as four banks of 32Mx72 including eight parity bits. The memory is configured
using four dual in-line memory module sockets, which will accept 168-pin dual in-line memory
modules (DIMMs) organized as 256MB (maximum) with a maximum access time of 10ns.
(SDRAM) organized as four banks of 32Mx72 including eight parity bits. The memory is configured
using four dual in-line memory module sockets, which will accept 168-pin dual in-line memory
modules (DIMMs) organized as 256MB (maximum) with a maximum access time of 10ns.
DMA C
ONTROLLER
The IRV-3702 SBC memory refresh and DMA functions are included in the System Controller chip that
includes the equivalence of two 82C37 DMA controllers. The two DMA controllers are cascaded to
provide four DMA channels for transfers to 8-bit peripherals (DMA1) and three channels for transfers
to 16-bit peripherals (DMA2). DMA2 Channel 0 provides the cascade interconnection for the two
DMA devices thereby maintaining IBM PC/AT compatibility. The DMA channel assignments are
listed below:
DMA Channel 0: Not Used (8-bit)
DMA Channel 1: Alternate for Multi-mode Parallel Port (8-bit)
DMA Channel 2: Floppy Disk (8-bit)
DMA Channel 3: Multi-mode Parallel Port (8-bit)
DMA Channel 5: Not Used (16-bit)
DMA Channel 6: Not Used (16-bit)
DMA Channel 7: Not Used (16-bit)
The DMA request (DRQx) and acknowledge (DACKx/) lines are available on the P1 98-pin edge
connector.
includes the equivalence of two 82C37 DMA controllers. The two DMA controllers are cascaded to
provide four DMA channels for transfers to 8-bit peripherals (DMA1) and three channels for transfers
to 16-bit peripherals (DMA2). DMA2 Channel 0 provides the cascade interconnection for the two
DMA devices thereby maintaining IBM PC/AT compatibility. The DMA channel assignments are
listed below:
DMA Channel 0: Not Used (8-bit)
DMA Channel 1: Alternate for Multi-mode Parallel Port (8-bit)
DMA Channel 2: Floppy Disk (8-bit)
DMA Channel 3: Multi-mode Parallel Port (8-bit)
DMA Channel 5: Not Used (16-bit)
DMA Channel 6: Not Used (16-bit)
DMA Channel 7: Not Used (16-bit)
The DMA request (DRQx) and acknowledge (DACKx/) lines are available on the P1 98-pin edge
connector.