SMSC SCH5027E User Manual
SMSC SCH5027E
PRODUCT PREVIEW
Revision 0.2 (02-11-09)
Data Brief
PRODUCT FEATURES
SCH5027E
Super I/O with
Temperature Sensing,
Quiet Auto Fan and
Glue Logic with PECI
Temperature Sensing,
Quiet Auto Fan and
Glue Logic with PECI
General Features
— 3.3 Volt Operation (SIO Block is 5 Volt Tolerant)
— LPC Interface
— Programmable Wake-up Event Interface
— PC99, PC2001 Compliant
— ACPI 2.0 Compliant
— Multiplexed Command, Address and Data Bus
— Serial IRQ Interface Compatible with Serialized IRQ
— LPC Interface
— Programmable Wake-up Event Interface
— PC99, PC2001 Compliant
— ACPI 2.0 Compliant
— Multiplexed Command, Address and Data Bus
— Serial IRQ Interface Compatible with Serialized IRQ
Support for PCI Systems
— PME Interface
— ISA Plug-and-Play Compatible Register Set
— 25 General Purpose Input/Output Pins
— System Management Interrupt
— ISA Plug-and-Play Compatible Register Set
— 25 General Purpose Input/Output Pins
— System Management Interrupt
PECI Interface
— Supports PECI REQUEST# and PECI AVAILABLE
signalling
AC Power Failure Recovery
Watchdog Timer
2.88MB Super I/O Floppy Disk Controller
— Licensed CMOS 765B Floppy Disk Controller
— Software and Register Compatible with SMSC's
— Software and Register Compatible with SMSC's
Proprietary 82077AA Compatible Core
— Supports One Floppy Drive
— Configurable Open Drain/Push-Pull Output Drivers
— Supports Vertical Recording Format
— 16-Byte Data FIFO
— 100% IBM® Compatibility
— Detects All Overrun and Underrun Conditions
— Sophisticated Power Control Circuitry (PCC) Including
— Configurable Open Drain/Push-Pull Output Drivers
— Supports Vertical Recording Format
— 16-Byte Data FIFO
— 100% IBM® Compatibility
— Detects All Overrun and Underrun Conditions
— Sophisticated Power Control Circuitry (PCC) Including
Multiple Powerdown Modes for Reduced Power
Consumption
Consumption
— DMA Enable Logic
— Data Rate and Drive Control Registers
— 480 Address, Up to Eight IRQ and Three DMA Options
— Support 3 Mode FDD
— Data Rate and Drive Control Registers
— 480 Address, Up to Eight IRQ and Three DMA Options
— Support 3 Mode FDD
Enhanced Digital Data Separator
— 2 Mbps, 1 Mbps, 500 Kbps, 300 Kbps, 250 Kbps Data
Rates
— Programmable Precompensation Modes
Serial Ports
— Two Full Function Serial Ports
— High Speed NS16C550A Compatible UARTs with
— High Speed NS16C550A Compatible UARTs with
Send/Receive 16-Byte FIFOs
— Supports 230k and 460k Baud
— Programmable Baud Rate Generator
— Modem Control Circuitry
— 480 Address and 15 IRQ Options
— Programmable Baud Rate Generator
— Modem Control Circuitry
— 480 Address and 15 IRQ Options
Infrared Port
— Multiprotocol Infrared Interface
— IrDA 1.0 Compliant
— SHARP ASK IR
— 480 Addresses, Up to 15 IRQ
— IrDA 1.0 Compliant
— SHARP ASK IR
— 480 Addresses, Up to 15 IRQ
Multi-Mode™ Parallel Port with ChiProtect™
— Standard Mode IBM PC/XT®, PC/AT®, and PS/2™
Compatible Bi-directional Parallel Port
— Enhanced Parallel Port (EPP) Compatible - EPP 1.7
and EPP 1.9 (IEEE 1284 Compliant)
— IEEE 1284 Compliant Enhanced Capabilities Port
(ECP)
— ChiProtect Circuitry for Protection
— 960 Address, Up to 15 IRQ and Three DMA Options
— 960 Address, Up to 15 IRQ and Three DMA Options
Keyboard Controller
— 8042 Software Compatible
— 8 Bit Microcomputer
— 2k Bytes of Program ROM
— 256 Bytes of Data RAM
— Four Open Drain Outputs Dedicated for
— 8 Bit Microcomputer
— 2k Bytes of Program ROM
— 256 Bytes of Data RAM
— Four Open Drain Outputs Dedicated for
Keyboard/Mouse Interface
— Asynchronous Access to Two Data Registers and One
Status Register
— Supports Interrupt and Polling Access
— 8 Bit Counter Timer
— Port 92 Support
— Fast Gate A20 and KRESET Outputs
— 8 Bit Counter Timer
— Port 92 Support
— Fast Gate A20 and KRESET Outputs
Motherboard GLUE Logic
— IDE Reset Output
— (4) Buffered PCI Reset Outputs with software controlled
— (4) Buffered PCI Reset Outputs with software controlled
reset capability - default transparent
— Front Panel Reset Debouncing and Power Good Signal
Generation
— Power Supply Turn On Circuitry with Support for power
button on PS/2 Keyboard
— Resume Reset Signal Generation
— SMBus Isolation Circuitry (2 sets external and 1 set
— SMBus Isolation Circuitry (2 sets external and 1 set
internal for Hardware Monitoring Block)
— SMBus 2.0 compliant interface for Hardware Monitoring
— LED Control (2)
— LED Control (2)
Fan Control
— 5 PWM (Pulse width Modulation) Outputs
— Low frequency and high frequency PWM support
— 6 Fan Tachometer Inputs
— Programmable automatic fan control based on
— Low frequency and high frequency PWM support
— 6 Fan Tachometer Inputs
— Programmable automatic fan control based on
temperature
— Interrupt Pin for out-of-limit Fantach Events
— Fantach events generate PME’s
— Fantach events generate PME’s