IBM Intel Xeon E5502 43W5986 User Manual
Product codes
43W5986
Intel® Xeon® Processor 5500 Series Datasheet, Volume 2
49
Register Description
2.5.8
PCISTS - PCI Status Register
The PCI Status register is a 16-bit status register that reports the occurrence of various
error events on this device's PCI interface.
error events on this device's PCI interface.
Device:
0
Function:
0-1
Offset:
06h
Device:
2
Function:
0-1, 4-5
Offset:
06h
Device:
3
Function:
0-2, 4
Offset:
06h
Device:
4-6
Function:
0-3
Offset:
06h
Bit
Type
Reset
Value
Description
15
RO
0
Detect Parity Error (DPE)
The host bridge does not implement this bit and is hardwired to a “0”. Writes to
The host bridge does not implement this bit and is hardwired to a “0”. Writes to
this bit position have no effect.
14
RO
0
Signaled System Error (SSE)
This bit is set to 1 when this device generates an SERR message over the bus
This bit is set to 1 when this device generates an SERR message over the bus
for any enabled error condition. If the host bridge does not signal errors using
this bit, this bit is hardwired to a “0” and is read-only. Writes to this bit position
have no effect.
13
RO
0
Received Master Abort Status (RMAS)
This bit is set when this device generates request that receives an Unsupported
This bit is set when this device generates request that receives an Unsupported
Request completion packet. Software clears the bit by writing 1 to it.
If this device does not receive Unsupported Request completion packets, the bit
If this device does not receive Unsupported Request completion packets, the bit
is hardwired to “0” and is read-only. Writes to this bit position have no effect.
12
RO
0
Received Target Abort Status (RTAS)
This bit is set when this device generates a request that receives a Completer
This bit is set when this device generates a request that receives a Completer
Abort completion packet. Software clears this bit by writing a 1 to it.
If this device does not receive Completer Abort completion packets, this bit is
If this device does not receive Completer Abort completion packets, this bit is
hardwired to “0” and read-only. Writes to this bit position have no effect.
11
RO
0
Signaled Target Abort Status (STAS)
This device will not generate a Target Abort completion or Special Cycle. This bit
This device will not generate a Target Abort completion or Special Cycle. This bit
is not implemented in this device and is hardwired to a “0”. Writes to this bit
position have no effect.
10:9
RO
0
DEVSEL Timing (DEVT)
These bits are hardwired to “00”. Writes to these bit positions have no effect.
These bits are hardwired to “00”. Writes to these bit positions have no effect.
This device does not physically connect to PCI bus X. These bits are set to “00”
(fast decode) so that optimum DEVSEL timing for PCI bus X is not limited by this
device.
8
RO
0
Master Data Parity Error Detected (DPD)
PERR signaling and messaging are not implemented by this bridge, therefore
PERR signaling and messaging are not implemented by this bridge, therefore
this bit is hardwired to “0”. Writes to this bit position have no effect.
7
RO
1
Fast Back-to-Back (FB2B)
This bit is hardwired to “1”. Writes to this bit position have no effect. This device
This bit is hardwired to “1”. Writes to this bit position have no effect. This device
is not physically connected to a PCI bus. This bit is set to 1 (indicating back-to-
back capabilities) so that the optimum setting for this PCI bus is not limited by
this device.
6
RO
0
Reserved
5
RO
0
66 MHz Capable
Does not apply to PCI Express. Must be hardwired to “0”.
Does not apply to PCI Express. Must be hardwired to “0”.