Lucent Technologies MN10285K User Manual

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General Description
MN102H Series Overview
Panasonic  Semiconductor  Development  Company
MN102H75K/F75K/85K/F85K LSI User Manual
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Panasonic
1
General Description
1.1
MN102H Series Overview
The 16-bit MN102H series is the high-speed linear addressing version of the 
MN10200 series. The new architecture in this series is designed for C-language 
programming and is based on a detailed analysis of the requirements for 
embedded applications. From miniaturization to power savings, it provides for a 
wide range of needs in user systems, surpassing all previous architectures in 
speed and functionality.
This series uses a load/store architecture for computing within the registers rather 
than the accumulator system for computing within the memory space, which 
Panasonic has used in most of its previous major series. The basic instructions 
are one byte/one machine cycle, drastically shrinking code size and improving 
compiler efficiency. The circuit is designed for submicron technology, providing 
optimized hardware and low system power consumption.
The devices in this series contain up to 16 megabytes of linear address space and 
enable highly efficient program development. In addition, the optimized 
hardware structure allows for low system-wide power consumption even in large 
systems.
1.2
MN102H Series Features
Designed for embedded applications, the MN102H series contains a flexible and 
optimized hardware architecture as well as a simple and efficient instruction set. 
It provides both economy and speed. This section provides the features of the 
MN102H series CPU.
High-speed signal processing
An internal multiplier multiplies two 16-bit registers for a 32-bit product in a 
single cycle. In addition, the hardware contains a saturation calculator to 
ensure that no signal processing is missed and to increase signal processing 
speed.
Linear addressing for large systems
The MN102H series provides up to 16 megabytes of linear address space. 
With linear addressing, the CPU does not detect any borders between 
memory banks, which provides an effective development environment. The 
hardware architecture is also optimized for large-scale designs. The memory 
is not divided into instruction and data areas, so operations can share 
instructions.