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Lucent Technologies MN10285K User Manual

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Closed-Caption Decoder
Closed-Caption Decoder Registers
Panasonic  Semiconductor  Development  Company
MN102H75K/F75K/85K/F85K LSI User Manual
246
Panasonic
HSEP1: HSYNC Separator Control Register 1
x’007ECE’
(HSEP1W
x’007EEE’)
HSFREQ[10:0]: Correction HSYNC frequency
Set the correction HSYNC cycle in this field in HSYNC separator sam-
pling clock units. The valid range is x’000’ to x’7FF’, and the recom-
mended setting is x’010C’.
HSEP2: HSYNC Separator Control Register 2
x’007ED0’
(HSEP2E
x’007EF0’)
HCLOSEE[9:0]: Start position for HSYNC detection
Set the position in HSYNC separator sampling clock units. The valid range 
is x’000’ to x’3FF’, and the recommended setting is x’00E4’.
FIELD: Field Detection Control Register
x’007ED2’
(FIELDW
x’007EF2’)
ODDEVEN: Field detection signal
0: Odd field
1: Even field
VPHASE[9:0]: Phase difference setting for VSYNC and HSYNC
Set the phase difference in HSYNC separator sampling clock units. The 
valid range is x’000’ to x’3FF’.
HLOCKLV: Sync Separator Detection Control Register 1
x’007ED4’
(HLOCKLVW
x’007EF4’)
HLOCKLV[8:0]: Sync separator detection threshold
This value is compared to the count of the corrected HSYNC. The valid 
range is x’000’ to x’1FF’, and the recommended setting is x’0008’.
HLOCKLV 
≤
 HSYNC count 
→
 asynchronous
HLOCKLV 
>
 HSYNC count 
→
 synchronous
Bit:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
—
—
—
—
—
HS
FREQ
10
HS
FREQ
9
HS
FREQ
8
HS
FREQ
7
HS
FREQ
6
HS
FREQ
5
HS
FREQ
4
HS
FREQ
3
HS
FREQ
2
HS
FREQ
1
HS
FREQ
0
Reset:
0
0
0
0
0
0
0
1
0
0
0
0
1
1
0
0
R/W:
R
R
R
R
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
—
—
—
—
—
—
H
CLOSE
E9
H
CLOSE
E8
H
CLOSE
E7
H
CLOSE
E6
H
CLOSE
E5
H
CLOSE
E4
H
CLOSE
E3
H
CLOSE
E2
H
CLOSE
E1
H
CLOSE
E0
Reset:
0
0
0
0
0
0
0
0
1
1
1
0
0
1
0
0
R/W:
R
R
R
R
R
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
ODD
EVEN
—
—
—
—
—
V
PHASE
9
V
PHASE
8
V
PHASE
7
V
PHASE
6
V
PHASE
5
V
PHASE
4
V
PHASE
3
V
PHASE
2
V
PHASE
1
V
PHASE
0
Reset:
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
R/W:
R
R
R
R
R
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
H
LOCK
LV8
H
LOCK
LV7
H
LOCK
LV6
H
LOCK
LV5
H
LOCK
LV4
H
LOCK
LV3
H
LOCK
LV2
H
LOCK
LV1
H
LOCK
LV0
Reset:
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
R/W:
R
R
R
R
R
R
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W