Lucent Technologies MN10285K User Manual

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The I

2

C bus controller contains the registers shown in table 13-3. See the page 

number indicated for register and bit descriptions.

■

The I

2

C bus controller allows software control, but implements communication 

timing and bus arbitration completely in the hardware.

♦

Arbitration: Controlled by the software, but implemented completely 
in the hardware.

♦

Bus busy: Checked by the hardware. This eliminates the need for the 
software to check whether the bus is busy. The program can request a 

transfer to the I

2

C bus at any time.

I2CDTRM

x’007E40’

I

2

C transmission data register

I2CDREC

x’007E42’

I

2

C reception data register

I2CMYAD

x’007E44’

I

2

C self address register

I2CCLK

x’007E46’

I

2

C clock control register

I2CBRST

x’007E48’

I

2

C bus reset register

I2CBSTS

x’007E4A’

I

2

C bus status register

SDA

Digital

filter

Data bus

controller

Parallel-to-serial

converter

Serial-to-parallel

converter

SCL

Digital

filter

Clock

controller

MSB

LSB

Transmission data register

MSB

LSB

Reception data register

Bus buffer

Address register

Clock register

ACK

BB

Address comparator

STO

LAB

STA

AAS

LRB

STS

MODE

Control register

Status register

I

2

C sequence controller

Register control

Bus busy logic
Arbitration logic
Clock prescaler

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