Intel Xeon Processor 3.6GHz FSB 800MHz 2MB BOX BX80546KG3600FU User Manual

Product codes

BX80546KG3600FU

Enhance performance for data-intensive
applications with PCI Express*

With the increase in the compute performance of the 64-bit Intel

Xeon processor with 2MB L2 cache, the I/O (input/output) rate at

which data can be supplied to the processor increases correspond-

ingly. As processors become faster, the rate at which data needs to

be supplied increases. In demanding computing situations, users

running compute- and I/O-intensive applications may bump up

against the maximum usable bandwidth afforded by PCI-X. Without

sufficient memory bandwidth, the processor can sit idle, waiting for

data to be transferred, which affects system performance. At the

same time, the industry is transitioning from a parallel I/O (e.g., SCSI,

ATA) towards a serial I/O (e.g., SATA, SAS) interconnect infrastructure.

A new serial I/O technology foundation is required to match the

performance and capabilities of these next-generation serial inter-

connects. PCI Express is the answer to both of these issues.

PCI Express is architected to have lower memory and I/O latency

compared to PCI. PCI Express is also capable of higher bandwidth

compared to today’s PCI or PCI-X solutions. Higher bandwidth means

more data can be transferred in the same unit of time. A PCI Express

x1 (“by 1”) link has a bi-directional peak bandwidth of 500 MB/s, while

x4 and x8 links are capable of 2 GB/s and 4 GB/s, respectively.

The lower latency and the increased bandwidth help deliver the

data speed required to fully utilize the processor’s capabilities.

Current legacy PCI-X adapters can still be used while transitioning

to new I/O adapters that take advantage of the inherent benefits

of this new serial I/O technology.

With the Intel

E7520 and Intel

E7320 chipsets, PCI Express

adapters have a direct path to either chipset’s memory controller

instead of having to go through a separate bridge component. With

the direct attach to the memory controller, two stages are removed.

This implementation minimizes the latency between the I/O adapter

and the memory controller for improved I/O performance.

In addition to the many benefits of PCI Express, it is also a common

I/O interface for mobile, desktop, workstation, storage, and network

technologies. This results in economies of scale, which in turn rapidly

drives down the cost of PCI Express solutions.

And as the industry transitions from a parallel to a serial I/O

infrastructure, users can confidently invest in new DP server

platforms supporting PCI Express technology. With their scalable

architecture, these platforms provide a smooth upgrade path

to 10 Gigabit-based technologies.

Save on power costs using Demand-Based Switching
(DBS) with Enhanced Intel SpeedStep

technology

Enhanced Intel SpeedStep

technology, a feature of the 64-bit Intel

Xeon processor with 2MB L2 cache, enables platform and software

power management features to lower average power consumption

while maintaining application performance. It can help reduce

average CPU power consumption by up to 25%, with minimal

performance impact

The processor’s operational states can vary based on usage. So when

utilization is high and maximum performance is desired, the processor

can be switched to a higher operational state automatically. When

usage is lower, transitioning to a lower operational state lowers the

average power-consumption while maintaining application perform-

ance. There is even a state for maximum power conservation during

system idle periods. Not only are power consumption levels reduced

during lower operational states, but system acoustics can also be

lowered by slowing down or halting fan operation entirely.

Improve security and reduce virus-related repairs
with Intel’s Execute Disable Bit functionality

Malicious buffer overflow attacks pose a significant security threat

to your business, increasing your IT resource demands and in some

cases destroying data. In a typical attack, a malicious worm creates

a flood of code that overwhelms the processor, allowing the worm

to propagate itself to the network and other computers. The Intel

Execute Disable Bit functionality can prevent certain classes of

malicious “buffer overflow” attacks when combined with a

supporting operating system.

Execute Disable Bit allows the processor to classify areas in memory

by where the application code can execute and where it cannot. When

a malicious worm attempts to insert code in the buffer, the processor

disables code execution, preventing damage or worm propagation.

Replacing older computers with Execute Disable Bit-enabled systems

can halt worm attacks, reducing the need for virus-related repairs.

In addition, Execute Disable Bit may eliminate the need for software

patches aimed at buffer overflow attacks.

In addition to the many benefits

of PCI Express, it is also a common

I/O interface for mobile, desktop,

workstation, storage and

network technologies.