Intel Xeon E7450 AD80582QH056003 Data Sheet
Product codes
AD80582QH056003
Electrical Specifications
22
Intel® Xeon® Processor 7400 Series Datasheet
outlines AGTL+ signals which include on-die termination (RTT) and those that
require external termination.
outlines non AGTL+ signals including open drain
signals.
provides signal reference voltages.
Note:
1.
Signals that have RTT in the package with 50 Ω pullup to V
TT
.
2.7
CMOS Asynchronous and Open Drain
Asynchronous Signals
Legacy input signals such as A20M#, IGNNE#, INIT#, SMI#, and STPCLK# utilize
CMOS input buffers. Legacy output signals such as FERR#/PBE#, IERR#, PROCHOT#,
THERMTRIP#, and TDO utilize open drain output buffers. All of the CMOS and Open
Drain signals are required to be asserted/deasserted for at least eight BCLKs in order
for the processor to recognize the proper signal state. See
CMOS input buffers. Legacy output signals such as FERR#/PBE#, IERR#, PROCHOT#,
THERMTRIP#, and TDO utilize open drain output buffers. All of the CMOS and Open
Drain signals are required to be asserted/deasserted for at least eight BCLKs in order
for the processor to recognize the proper signal state. See
and
for the DC and AC specifications. See
for additional timing
requirements for entering and leaving the low power states.
2.8
Test Access Port (TAP) Connection
Due to the voltage levels supported by other components in the Test Access Port (TAP)
logic, it is recommended that the processor(s) be first in the TAP chain and followed by
any other components within the system. A translation buffer should be used to
connect to the rest of the chain unless one of the other components is capable of
accepting an input of the appropriate voltage. Similar considerations must be made for
TCK, TMS, and TRST#. Two copies of each signal may be required with each driving a
different voltage level.
logic, it is recommended that the processor(s) be first in the TAP chain and followed by
any other components within the system. A translation buffer should be used to
connect to the rest of the chain unless one of the other components is capable of
accepting an input of the appropriate voltage. Similar considerations must be made for
TCK, TMS, and TRST#. Two copies of each signal may be required with each driving a
different voltage level.
Table 2-5.
AGTL+ Signal Description Table
AGTL+ signals with R
TT
AGTL+ signals with no R
TT
A[39:3]#, ADS#, ADSTB[1:0]#, AP[1:0]#, BINIT#,
BNR#, BPRI#, D[63:0]#, DBI[3:0]#, DBSY#,
DEFER#, DP[3:0]#, DRDY#, DSTBN[3:0]#,
DSTBP[3:0]#, HIT#, HITM#, LOCK#, MCERR#,
REQ[4:0]#, RS[2:0]#, RSP#, TRDY#
BPM[5:0]#, BPMb[3:0]#, RESET#, BR[1:0]#
Table 2-6.
Non AGTL+ Signal Description Table
Signals with R
TT
Signals with no R
TT
A20M#, BCLK[1:0], BSEL[2:0], COMP[3:0], FERR#/
PBE#, FORCEPR#, GTLREF_ADD_MID,
GTLREF_ADD_END, GTLREF_DATA_MID,
GTLREF_DATA_END, IERR#, IGNNE#, INIT#, LINT0/
INTR, LINT1/NMI, LL_ID[1:0], PROC_ID[1:0], PECI,
PROCHOT#, PWRGOOD, SKTOCC#, SMI#, STPCLK#,
TCK, TDI, TDO, TESTHI[1:0], TESTIN1, TESTIN2,
THERMTRIP#, TMS, TRST#, VCC_SENSE, VCC_SENSE2,
VID[6:1], VSS_SENSE, VSS_SENSE2, VTT_SEL
Table 2-7.
Signal Reference Voltages
GTLREF
CMOS
A[39:3]#, ADS#, ADSTB[1:0]#, AP[1:0]#, BINIT#,
BNR#, BPM[5:0]#, BPMb[3:0]#, BPRI#, BR[1:0]#,
D[63:0]#, DBI[3:0]#, DBSY#, DEFER#, DP[3:0]#,
DRDY#, DSTBN[3:0]#, DSTBP[3:0]#, HIT#,
HITM#, LOCK#, MCERR#, RESET#, REQ[4:0]#,
RS[2:0]#, RSP#, TRDY#
A20M#, FORCEPR#, LINT0/INTR, LINT1/NMI, IGNNE#,
INIT#, PWRGOOD, SMI#, STPCLK#, TCK, TDI, TMS,
TRST#