Intel Xeon E7440 AD80583QH056007 Data Sheet

Intel® Xeon® Processor 7400 Series Datasheet

87

SM_WP

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WP (Write Protect) can be used to write protect the Scratch EEPROM. The Scratch 

EEPROM is write-protected when this input is pulled high to SM_VCC. The 

processor includes a 10 kΩ pull-down resistor to V

SS

 for this signal.

SMI#

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SMI# (System Management Interrupt) is asserted asynchronously by system logic. 

On accepting a System Management Interrupt, processors save the current state 

and enter System Management Mode (SMM). An SMI Acknowledge transaction is 

issued, and the processor begins program execution from the SMM handler.
If SMI# is asserted during the deassertion of RESET# the processor will tri-state 

its outputs. See 

STPCLK#

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STPCLK# (Stop Clock), when asserted, causes processors to enter a low power 

Stop-Grant state. The processor issues a Stop-Grant Acknowledge transaction, and 

stops providing internal clock signals to all processor core units except the FSB and 

APIC units. The processor continues to snoop bus transactions and service 

interrupts while in Stop-Grant state. When STPCLK# is deasserted, the processor 

restarts its internal clock to all units and resumes execution. The assertion of 

STPCLK# has no effect on the bus clock; STPCLK# is an asynchronous input.

TCK

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TCK (Test Clock) provides the clock input for the processor Test Bus (also known as 

the Test Access Port).

TDI

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TDI (Test Data In) transfers serial test data into the processor. TDI provides the 

serial input needed for JTAG specification support.

TDO

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TDO (Test Data Out) transfers serial test data out of the processor. TDO provides 

the serial output needed for JTAG specification support.

TESTHI[1:0]

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TESTHI[1:0] must be connected to a V

TT

 power source through a resistor for 

proper processor operation. Refer to 

 for TESTHI grouping restrictions.

TESTIN1
TESTIN2

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TESTIN1 must be connected to a VTT power source through a resistor as well as to 

the TESTIN2 pin of the same socket for proper processor operation.
TESTIN2 must be connected to a VTT power source through a resistor as well as to 

the TESTIN1 pin of the same socket for proper processor operation.
Refer to 

 for TESTIN restrictions.

THERMTRIP#

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Assertion of THERMTRIP# (Thermal Trip) indicates the processor junction 

temperature has reached a temperature beyond which permanent silicon damage 

may occur. Measurement of the temperature is accomplished through an internal 

thermal sensor. Upon assertion of THERMTRIP#, the processor will shut off its 

internal clocks (thus halting program execution) in an attempt to reduce the 

processor junction temperature. To protect the processor, its core voltage (V

CC

) 

must be removed following the assertion of THERMTRIP#. See 

 and 

 for the appropriate power down sequence and timing requirements. 

Intel is currently evaluating whether V

TT

 must also be removed.

Driving of the THERMTRIP# signals is enabled within 10 ms of the assertion of 

PWRGOOD and is disabled on de-assertion of PWRGOOD. Once activated, 

THERMTRIP# remains latched until PWRGOOD is de-asserted. While the de-

assertion of the PWRGOOD signal will de-assert THERMTRIP#, if the processor’s 

junction temperature remains at or above the trip level, THERMTRIP# will again be 

asserted within 10 ms of the assertion of PWRGOOD.

TMS

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TMS (Test Mode Select) is a JTAG specification support signal used by debug tools.

TRDY#

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TRDY# (Target Ready) is asserted by the target to indicate that it is ready to 

receive a write or implicit writeback data transfer. TRDY# must connect the 

appropriate pins of all FSB agents.

TRST#

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TRST# (Test Reset) resets the Test Access Port (TAP) logic. TRST# must be driven 

low during power on Reset.

V

CCPLL

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The Intel® Xeon® Processor 7400 Series implement an on-die PLL filter solution. 

The V

CCPLL

 input is used as a PLL supply voltage.

VCC_SENSE
VCC_SENSE2

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VCC_SENSE and VCC_SENSE2 provides an isolated, low impedance connection to 

the processor core power and ground. This signal should be connected to the 

voltage regulator feedback signal, which insures the output voltage (that is, 

processor voltage) remains within specification. Please see the applicable platform 

design guide for implementation details.