Intel C2D Mobile T5800 LF80537GG041F User Manual

Datasheet

19

The processor features Enhanced Intel SpeedStep Technology. Following are the key 

features of Enhanced Intel SpeedStep Technology:

• Multiple voltage and frequency operating points provide optimal performance at the 

lowest power. 

• Voltage and frequency selection is software-controlled by writing to processor 

MSRs:

— If the target frequency is higher than the current frequency, V

CC

 is ramped up 

in steps by placing new values on the VID pins, and the PLL then locks to the 

new frequency.

— If the target frequency is lower than the current frequency, the PLL locks to the 

new frequency and the V

CC

 is changed through the VID pin mechanism.

— Software transitions are accepted at any time. If a previous transition is in 

progress, the new transition is deferred until the previous transition completes.

• The processor controls voltage ramp rates internally to ensure glitch-free 

transitions.

• Low transition latency and large number of transitions possible per second:

— Processor core (including L2 cache) is unavailable for up to 10 μs during the 

frequency transition.

— The bus protocol (BNR# mechanism) is used to block snooping.

• Improved Intel® Thermal Monitor mode:

— When the on-die thermal sensor indicates that the die temperature is too high 

the processor can automatically perform a transition to a lower frequency and 

voltage specified in a software-programmable MSR.

— The processor waits for a fixed time period. If the die temperature is down to 

acceptable levels, an up-transition to the previous frequency and voltage point 

occurs.

— An interrupt is generated for the up and down Intel Thermal Monitor transitions 

enabling better system-level thermal management. 

• Enhanced thermal management features:

— Digital Thermal Sensor and Out of Specification detection.
— Intel Thermal Monitor 1 (TM1) in addition to Intel Thermal Monitor 2 (TM2) in 

case of unsuccessful TM2 transition.

— Dual-core thermal management synchronization. 

Each core in the dual-core processor implements an independent MSR for controlling 

Enhanced Intel SpeedStep Technology, but both cores must operate at the same 

frequency and voltage. The processor has performance state coordination logic to 

resolve frequency and voltage requests from the two cores into a single frequency and 

voltage request for the package as a whole. If both cores request the same frequency 

and voltage, then the processor will transition to the requested common frequency and 

voltage. If the two cores have different frequency and voltage requests, then the 

processor will take the highest of the two frequencies and voltages as the resolved 

request and transition to that frequency and voltage.

The processor also supports Dynamic FSB Frequency Switching and Intel Dynamic 

Acceleration Technology mode on select SKUs. The operating system can take 

advantage of these features and request a lower operating point called SuperLFM (due 

to Dynamic FSB Frequency Switching) and a higher operating point Intel Dynamic 

Acceleration Technology mode.