IBM Intel Xeon E5502 46D1350 User Manual

Product codes

46D1350

Intel® Xeon® Processor 5500 Series Datasheet, Volume 2

Contents

Introduction ............................................................................................................ 15
1.1

Terminology ..................................................................................................... 15
1.1.1

Processor Terminology .......................................................................... 15

1.2

References ....................................................................................................... 17

Register Description ................................................................................................ 19
2.1

2.2

Platform Configuration Structure ......................................................................... 20

2.3

Device Mapping................................................................................................. 21

2.4

Detailed Configuration Space Maps ...................................................................... 23

2.5

PCI Standard Registers ...................................................................................... 45
2.5.1

VID - Vendor Identification Register ........................................................ 45

2.5.2

DID - Device Identification Register......................................................... 45

2.5.3

RID - Revision Identification Register....................................................... 46

2.5.4

CCR - Class Code Register ..................................................................... 46

2.5.5

HDR - Header Type Register................................................................... 47

2.5.6

SID/SVID - Subsystem Identity/Subsystem Vendor

Identification Register ........................................................................... 47

2.5.7

PCICMD - Command Register ................................................................. 48

2.5.8

PCISTS - PCI Status Register.................................................................. 49

2.6

Generic Non-core Registers ................................................................................ 50
2.6.1

MAXREQUEST_LC ................................................................................. 50

2.6.2

MAXREQUEST_LS ................................................................................. 51

2.6.3

MAXREQUEST_LL.................................................................................. 51

2.6.4

MAX_RTIDS ......................................................................................... 51

2.6.5

DESIRED_CORES.................................................................................. 52

2.6.6

MEMLOCK_STATUS ............................................................................... 52

2.6.7

MC_CFG_CONTROL ............................................................................... 53

2.6.8

POWER_CNTRL_ERR_STATUS................................................................. 53

2.6.9

CURRENT_UCLK_RATIO ......................................................................... 54

2.6.10

MIRROR_PORT_CTL .............................................................................. 55

2.6.11

MIP_PH_CTR_L0

MIP_PH_CTR_L1 ................................................................................... 55

2.6.12

MIP_PH_PRT_L0

MIP_PH_PRT_L1 ................................................................................... 56

2.7

SAD - System Address Decoder Registers ............................................................. 56
2.7.1

SAD_PAM0123 ..................................................................................... 56

2.7.2

SAD_PAM456 ....................................................................................... 58

2.7.3

SAD_HEN ............................................................................................ 59

2.7.4

SAD_SMRAM ........................................................................................ 59

2.7.5

SAD_PCIEXBAR .................................................................................... 60

SAD_DRAM_RULE_7.............................................................................. 60