Intel X5272 AT80573KL0966M Data Sheet

15

Most Dual-Core Intel® Xeon® Processor 5200 Series FSB signals use Assisted Gunning 
Transceiver Logic (AGTL+) signaling technology. This technology provides improved 
noise margins and reduced ringing through low voltage swings and controlled edge 
rates. AGTL+ buffers are open-drain and require pull-up resistors to provide the high 
logic level and termination. AGTL+ output buffers differ from GTL+ buffers with the 
addition of an active PMOS pull-up transistor to “assist” the pull-up resistors during the 
first clock of a low-to-high voltage transition. Platforms implement a termination 
voltage level for AGTL+ signals defined as V

TT

. Because platforms implement separate 

power planes for each processor (and chipset), separate V

CC

 and V

TT

 supplies are 

necessary. This configuration allows for improved noise tolerance as processor 
frequency increases. Speed enhancements to data and address buses have made 
signal integrity considerations and platform design methods even more critical than 
with previous processor families. Design guidelines for the processor FSB are detailed 
in the appropriate platform design guidelines (refer to 

The AGTL+ inputs require reference voltages (GTLREF_DATA and GTLREF_ADD) which 
are used by the receivers to determine if a signal is a logical 0 or a logical 1. 
GTLREF_DATA is used for the 4X front side bus signaling group and GTLREF_ADD is 
used for the 2X and common clock front side bus signaling groups. Both GTLREF_DATA 
and GTLREF_ADD must be generated on the baseboard (See 

 for 

GTLREF_DATA and GTLREF_ADD specifications). Refer to the applicable platform design 
guidelines for details. Termination resistors (R

TT

) for AGTL+ signals are provided on the 

processor silicon and are terminated to V

TT

. The on-die termination resistors are always 

enabled on the Dual-Core Intel® Xeon® Processor 5200 Series to control reflections on 
the transmission line. Intel chipsets also provide on-die termination, thus eliminating 
the need to terminate the bus on the baseboard for most AGTL+ signals.

Some FSB signals do not include on-die termination (R

TT

) and must be terminated on 

the baseboard. See 

 for details regarding these signals.

The AGTL+ bus depends on incident wave switching. Therefore, timing calculations for 
AGTL+ signals are based on flight time as opposed to capacitive deratings. Analog 
signal simulation of the FSB, including trace lengths, is highly recommended when 
designing a system. Contact your Intel Field Representative to obtain the Dual-Core 
Intel® Xeon® Processor 5200 Series signal integrity models, which includes buffer and 
package models.

For clean on-chip processor core power distribution, the processor has 223 V

CC

 (power) 

and 273 V

SS

 

(ground) inputs. All V

CC

 lands must be connected to the processor power 

plane, while all V

SS

 lands must be connected to the system ground plane. The 

processor V

CC

 lands must be supplied with the voltage determined by the processor 

Voltage IDentification (VID) signals. See 

 for VID definitions.