Intel X5272 AT80573KL0966M Data Sheet

96

When the STPCLK# pin is asserted, the Stop-Grant state of the processor is entered no 
later than 20 bus clocks after the response phase of the processor issued Stop Grant 
Acknowledge special bus cycle. Once the STPCLK# pin has been asserted, it may only 
be deasserted once the processor is in the Stop Grant state. All processor cores will 
enter the Stop-Grant state once the STPCLK# pin is asserted. Additionally, all processor 
cores must be in the Stop Grant state before the deassertion of STPCLK#.

Since the AGTL+ signal pins receive power from the front side bus, these pins should 
not be driven (allowing the level to return to V

TT

) for minimum power drawn by the 

termination resistors in this state. In addition, all other input pins on the front side bus 
should be driven to the inactive state.

BINIT# will not be serviced while the processor is in Stop-Grant state. The event will be 
latched and can be serviced by software upon exit from the Stop Grant state.

RESET# will cause the processor to immediately initialize itself, but the processor will 
stay in Stop-Grant state. A transition back to the Normal state will occur with the de-
assertion of the STPCLK# signal.

A transition to the Grant Snoop state will occur when the processor detects a snoop on 
the front side bus (see 

While in the Stop-Grant state, SMI#, INIT#, BINIT# and LINT[1:0] will be latched by 
the processor, and only serviced when the processor returns to the Normal state. Only 
one occurrence of each event will be recognized upon return to the Normal state.

While in Stop-Grant state, the processor will process snoops on the front side bus and it 
will latch interrupts delivered on the front side bus.

The PBE# signal can be driven when the processor is in Stop-Grant state. PBE# will be 
asserted if there is any pending interrupt latched within the processor. Pending 
interrupts that are blocked by the EFLAGS.IF bit being clear will still cause assertion of 
PBE#. Assertion of PBE# indicates to system logic that it should return the processor to 
the Normal state.

The Extended HALT Snoop state is used in conjunction with the Extended HALT state. If 
the Extended HALT state is not enabled in the BIOS, the default Snoop state entered 
will be the HALT Snoop state. Refer to the sections below for details on HALT Snoop 
state, Stop Grant Snoop state and Extended HALT Snoop state.

The processor will respond to snoop or interrupt transactions on the front side bus 
while in Stop-Grant state or in HALT state. During a snoop or interrupt transaction, the 
processor enters the HALT/Grant Snoop state. The processor will stay in this state until 
the snoop on the front side bus has been serviced (whether by the processor or another 
agent on the front side bus) or the interrupt has been latched. After the snoop is 
serviced or the interrupt is latched, the processor will return to the Stop-Grant state or 
HALT state, as appropriate.