Intel Xeon E5430 BX80574E5430 Data Sheet

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GTLREF_DATA_MID
GTLREF_DATA_END

I

GTLREF_DATA determines the signal reference level for AGTL+ data 

input lands. GTLREF_DATA is used by the AGTL+ receivers to 

determine if a signal is a logical 0 or a logical 1. Please refer to 

 and the appropriate platform design guidelines for 

additional details.

HIT#
HITM#

I/O
I/O

HIT# (Snoop Hit) and HITM# (Hit Modified) convey transaction snoop 

operation results. Any FSB agent may assert both HIT# and HITM# 

together to indicate that it requires a snoop stall, which can be 

continued by reasserting HIT# and HITM# together.

3

IERR#

O

IERR# (Internal Error) is asserted by a processor as the result of an 

internal error. Assertion of IERR# is usually accompanied by a 

SHUTDOWN transaction on the processor FSB. This transaction may 

optionally be converted to an external error signal (e.g., NMI) by 

system core logic. The processor will keep IERR# asserted until the 

assertion of RESET#.
This signal does not have on-die termination.

2

IGNNE#

I

IGNNE# (Ignore Numeric Error) is asserted to force the processor to 

ignore a numeric error and continue to execute noncontrol floating-

point instructions. If IGNNE# is deasserted, the processor generates 

an exception on a noncontrol floating-point instruction if a previous 

floating-point instruction caused an error. IGNNE# has no effect when 

the NE bit in control register 0 (CR0) is set.
IGNNE# is an asynchronous signal. However, to ensure recognition of 

this signal following an I/O write instruction, it must be valid along 

with the TRDY# assertion of the corresponding I/O write bus 

transaction.

2

INIT#

I

INIT# (Initialization), when asserted, resets integer registers inside 

all processors without affecting their internal caches or floating-point 

registers. Each processor then begins execution at the power-on 

Reset vector configured during power-on configuration. The processor 

continues to handle snoop requests during INIT# assertion. INIT# is 

an asynchronous signal and must connect the appropriate pins of all 

processor FSB agents.

2

LINT[1:0]

I

LINT[1:0] (Local APIC Interrupt) must connect the appropriate pins 

of all FSB agents. When the APIC functionality is disabled, the 

LINT0/INTR signal becomes INTR, a maskable interrupt request 

signal, and LINT1/NMI becomes NMI, a nonmaskable interrupt. INTR 

and NMI are backward compatible with the signals of those names on 

the Pentium

®

 processor. Both signals are asynchronous.

These signals must be software configured via BIOS programming of 

the APIC register space to be used either as NMI/INTR or LINT[1:0]. 

Because the APIC is enabled by default after Reset, operation of 

these pins as LINT[1:0] is the default configuration.

2

LL_ID[1:0]

O

The LL_ID[1:0] signals are used to select the correct loadline slope 

for the processor. These signals are not connected to the processor 

die.

LOCK#

I/O

LOCK# indicates to the system that a transaction must occur 

atomically. This signal must connect the appropriate pins of all 

processor FSB agents. For a locked sequence of transactions, LOCK# 

is asserted from the beginning of the first transaction to the end of 

the last transaction.
When the priority agent asserts BPRI# to arbitrate for ownership of 

the processor FSB, it will wait until it observes LOCK# deasserted. 

This enables symmetric agents to retain ownership of the processor 

FSB throughout the bus locked operation and ensure the atomicity of 

lock.

3