Intel X7460 AD80582KH067007 Data Sheet

Intel® Xeon® Processor 7400 Series Datasheet

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The Intel® Xeon® Processor 7400 Series obtains its PECI address based on the 

processors APIC ID[4:3] at power on. APIC ID[4:3] is also known as the Cluster 

ID[1:0]. The Cluster ID[1:0] is set, by the chipset, by asserting the power-on 

configuration (POC) signals A[12:11]# at the deassertion of RESET#.

The PECI address for the Intel® Xeon® Processor 7400 Series = 0x30 + Cluster 

ID[0:1] 

. 

The initial Cluster ID assigned to each socket must be unique to ensure a unique PECI 

address is assigned to each socket. The Cluster ID may be changed via the XAPIC ID 

register.

The default PECI device address for the Intel® 7300 chipset FSB0 is 0x30.

The default PECI device address for the Intel 7300 chipset FSB1 is 0x32.

The default PECI device address for the Intel 7300 chipset FSB2 is 0x31.

The default PECI device address for the Intel 7300 chipset FSB3 is 0x33.

The power-on-configuration (POC) settings of third-party chipsets may produce 

different PECI addresses than those shown above. Thermal designers should consult 

their third party chipset designers for the default configured PECI addresses or power-

on configuration method.

Please note that each address also supports two domains (Domain 0 and Domain 1). 

For more information on PECI domains, please refer to the Platform Environment 

Control Interface Specification.

1.

The Cluster ID bit order is reversed [0:1] for the PECI address calculation.

PECI command support is covered in detail in RS - Platform Environment Control 
Interface (PECI) Specification. Please refer to this document for details on supported 
PECI command function and codes

PECI is largely a fault tolerant interface, including noise immunity and error checking 
improvements over other comparable industry standard interfaces. The PECI client is 
as reliable as the device that it is embedded in, and thus given operating conditions 
that fall under the specification, the PECI will always respond to requests and the 
protocol itself can be relied upon to detect any transmission failures. There are, 
however, certain scenarios where the PECI is known to be unresponsive.

Prior to a power on RESET# and during RESET# assertion, PECI is not guaranteed to 
provide reliable thermal data. System designs should implement a default power-on 
condition that ensures proper processor operation during the time frame when reliable 
data is not available via PECI.

To protect platforms from potential operational or safety issues due to an abnormal 
condition on PECI, the Host controller should take action to protect the system from 
possible damaging states. If the Host controller cannot complete a valid PECI 
transactions of GetTemp0() with a given PECI device over 3 consecutive failed 
transactions or a one second max specified interval, then it should take appropriate