Fujitsu FS PRIMEPOWER 2500 SO8 BASE CABINET 128CPU D:GPK25-GA72 User Manual

Data Sheet 

⏐ Issue: March 2005⏐ PRIMEPOWER 2500 

Page 2 / 4 

 
PRIMEPOWER 2500 System Functions 

 
„  Enhanced SPARC64™V processor architecture implemented in latest copper technology with 1.82 GHz and fast 3MB level 2 

cache on chip 

„  XA system architecture with up to 64 SPARC64™V processors in the basic system cabinet and up to 128 SPARC64™V 

processors in the extended system cabinet   

„  Up to 15 independent physical system partitions (PPAR) or extended partitions (XPAR) 
„  Up to 4 extended partitions (XPAR) per system board 
„  Up to 32 PCI/disk boxes (2 per system board) each with 10 PCI slots in 1-4 I/O cabinets. All PCI slots are hot plug able 
„  Each PCI/disk box with 4 disk bays 
„  Redundant high speed crossbar Interconnect with large bandwidth of up to 133 GB/s (520 MHz crossbar clock) 
„  Redundant system clock 
„  Optional Dual Power Feed for redundancy of power phases 
„  Redundant and hot swap able hard disks, fans and power supplies  
„  Hot plug able system boards, system board components and PCI controllers  
„  System boards and PCI controllers can be replaced in separate partitions without affecting other partitions   
„  Dynamic reconfiguration of system boards and system board components during operation 
„  Automatic restart in case of failures (ASR = Auto Shutdown and Recovery) after reconfiguring of the failed parts 
„  System Control Facility (SCF)  and ServerView for system management, diagnostic and control 
„  System cabinet with small footprint and flexible usable 19 inch rack space (4HU)  
„  2 system cabinets for either up to 64 processors (basic cabinet) or 128 processors (extended cabinet). Fieldupgrade for basic 

to extended cabinet enhancement 

„  Up to 4 I/O cabinets for PCI/disk boxes (8 per cabinet) 

 
SPARC64 

TM 

V – Processor Functions (1.30 GHz and 1.82GHz) 

 
 

„ Super-scalar processing 
„ VIS

TM

 – Visual Instruction Set 

„  64-bit virtual address space 
„  7 execution units (2 load store, 2 ALU, 2 FP, 1 branch) 
„  Up to 4 instructions can be completed with each cycle 
„  SMP – cache coherency support 
„  2x 128 KB on-chip level-1 low latency cache 
„  4 way 16K-entry  branch history table 
„  Optimized branch prediction method 
„  Concurrent out-of-order execution 
„  ECC (Error Correction Code) for  

„ level-1-data-cache,  
„ level-2-cache,  
„  high speed interconnect  
„ main memory 

„  Parity for  

„ CPU-registers,  
„  CPU-core (data path and ALUs) 
„  level-1-instuction-cache 
„  TLB (Translation Look-aside Buffer) 

„  Duplicated Tags for Level-1 instruction-  and data-cache 
„  Automatic, in hardware implemented recovery of complete instructions in case of sporadic one bit errors within CPU core 

(AIR = Automatic Instruction Retry) 

„  Automatic error degradation for level 1 and level 2 caches and TLB in case of sporadic one bit errors (cache way 

degradation)  

„  Functions 1.30GHz processor 

„  2 MB 4-way joint low latency on-chip level-2 cache 
„  191 Mio. Transistors, 130nm copper technology 
„  Instruction TLB:  

1024 entry, 2-way, set associative 
 
 

„  Data TLB  

1024 entry, 2-way, set associative 

„  Functions 1.82GHz processor 

„  3 MB 3-way joint low latency on-chip level-2 cache 
„  400 Mio. Transistors, 90nm copper technology 
„  Instruction TLB:  

   1024 entry, 2-way, 8KB pages 
+ 1024 entry, 2-way, 4MB pages 
+ 32 entry, full associative 64KB, 512KB and locked pages  

„  Data TLB  

   1024 entry, 2-way, 8KB pages 
+ 1024 entry, 2-way, 4MB pages 
+ 32 entry, full associative 64KB, 512KB and locked pages