Intel E5400 AT80571PG0682ML Data Sheet
Product codes
AT80571PG0682ML
Datasheet
67
Land Listing and Signal Descriptions
DEFER#
Input
DEFER# is asserted by an agent to indicate that a transaction
cannot be ensured in-order completion. Assertion of DEFER# is
normally the responsibility of the addressed memory or input/
output agent. This signal must connect the appropriate pins/lands
of all processor FSB agents.
cannot be ensured in-order completion. Assertion of DEFER# is
normally the responsibility of the addressed memory or input/
output agent. This signal must connect the appropriate pins/lands
of all processor FSB agents.
DPRSTP#
Input
DPRSTP#, when asserted on the platform, causes the processor to
transition from the Deep Sleep State to the Deeper Sleep state. To
return to the Deep Sleep State, DPRSTP# must be deasserted. Use
of the DPRSTP# pin, and corresponding low power state, requires
chipset support and may not be available on all platforms.
NOTE: Some processors may not have the Deeper Sleep State
transition from the Deep Sleep State to the Deeper Sleep state. To
return to the Deep Sleep State, DPRSTP# must be deasserted. Use
of the DPRSTP# pin, and corresponding low power state, requires
chipset support and may not be available on all platforms.
NOTE: Some processors may not have the Deeper Sleep State
enabled, refer to the Specification Update for specific sku
and stepping guidance.
and stepping guidance.
DPSLP#
Input
DPSLP#, when asserted on the platform, causes the processor to
transition from the Sleep State to the Deep Sleep state. To return
to the Sleep State, DPSLP# must be deasserted. Use of the
DPSLP# pin, and corresponding low power state, requires chipset
support and may not be available on all platforms.
NOTE: Some processors may not have the Deep Sleep State
transition from the Sleep State to the Deep Sleep state. To return
to the Sleep State, DPSLP# must be deasserted. Use of the
DPSLP# pin, and corresponding low power state, requires chipset
support and may not be available on all platforms.
NOTE: Some processors may not have the Deep Sleep State
enabled, refer to the Specification Update for specific
processor and stepping guidance.
processor and stepping guidance.
DRDY#
Input/
Output
DRDY# (Data Ready) is asserted by the data driver on each data
transfer, indicating valid data on the data bus. In a multi-common
clock data transfer, DRDY# may be de-asserted to insert idle
clocks. This signal must connect the appropriate pins/lands of all
processor FSB agents.
transfer, indicating valid data on the data bus. In a multi-common
clock data transfer, DRDY# may be de-asserted to insert idle
clocks. This signal must connect the appropriate pins/lands of all
processor FSB agents.
DSTBN[3:0]#
Input/
Output
DSTBN[3:0]# are the data strobes used to latch in D[63:0]#.
DSTBP[3:0]#
Input/
Output
DSTBP[3:0]# are the data strobes used to latch in D[63:0]#.
FC0/BOOTSELECT
Other
FC0/BOOTSELECT is not used by the processor. When this land is
tied to V
tied to V
SS
previous processors based on the Intel NetBurst
®
microarchitecture should be disabled and prevented from booting.
FCx
Other
FC signals are signals that are available for compatibility with other
processors.
processors.
Table 25.
Signal Description (Sheet 4 of 10)
Name
Type
Description
Signals
Associated Strobe
D[15:0]#, DBI0#
DSTBN0#
D[31:16]#, DBI1#
DSTBN1#
D[47:32]#, DBI2#
DSTBN2#
D[63:48]#, DBI3#
DSTBN3#
Signals
Associated Strobe
D[15:0]#, DBI0#
DSTBP0#
D[31:16]#, DBI1#
DSTBP1#
D[47:32]#, DBI2#
DSTBP2#
D[63:48]#, DBI3#
DSTBP3#