Intel Xeon® Processor X3430 (8M Cache, 2.40 GHz) BX80605X3430 User Manual
Product codes
BX80605X3430
System Address Map
296
Intel® Xeon® Processor 3400 Series Datasheet, Volume 2
5.8.3
Intel
®
VT-d Address Map Implications
Intel VT-d applies only to inbound memory transactions. Inbound I/O and configuration
transactions are not affected by Intel VT-d. Inbound I/O, configuration and message
decode and forwarding happens the same whether Intel VT-d is enabled or not. For
memory transaction decode, the host address map in Intel VT-d corresponds to the
address map discussed earlier in the chapter and all addresses after translation are
subject to the same address map rule checking (and error reporting) as in the non-Intel
VT-d mode. There is not a fixed guest address map that IIO Intel VT-d hardware can
rely upon (except that the guest domain addresses cannot go beyond the guest
address width specified using the GPA_LIMIT register); that is, it is OS dependent. IIO
converts all incoming memory guest addresses to host addresses and then applies the
same set of memory address decoding rules as described earlier. In addition to the
address map and decoding rules previously discussed, IIO also supports an additional
memory range called the VTBAR range and this range is used to handle accesses to
Intel VT-d related chipset registers. Only aligned DWord/QWord accesses are allowed to
this region. Only outbound and SMBus/JTAG accesses are allowed to this range and
also these can only be accesses outbound from Intel QuickPath Interconnect. Inbound
accesses to this address range are completer aborted by the IIO.
transactions are not affected by Intel VT-d. Inbound I/O, configuration and message
decode and forwarding happens the same whether Intel VT-d is enabled or not. For
memory transaction decode, the host address map in Intel VT-d corresponds to the
address map discussed earlier in the chapter and all addresses after translation are
subject to the same address map rule checking (and error reporting) as in the non-Intel
VT-d mode. There is not a fixed guest address map that IIO Intel VT-d hardware can
rely upon (except that the guest domain addresses cannot go beyond the guest
address width specified using the GPA_LIMIT register); that is, it is OS dependent. IIO
converts all incoming memory guest addresses to host addresses and then applies the
same set of memory address decoding rules as described earlier. In addition to the
address map and decoding rules previously discussed, IIO also supports an additional
memory range called the VTBAR range and this range is used to handle accesses to
Intel VT-d related chipset registers. Only aligned DWord/QWord accesses are allowed to
this region. Only outbound and SMBus/JTAG accesses are allowed to this range and
also these can only be accesses outbound from Intel QuickPath Interconnect. Inbound
accesses to this address range are completer aborted by the IIO.
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