Intel Pentium 4 80528PC017G0K User Manual

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DRDY#

Input/

Output

DRDY# (Data Ready) is asserted by the data driver on each data transfer, 
indicating valid data on the data bus. In a multi-common clock data transfer, DRDY# 
may be deasserted to insert idle clocks. This signal must connect the appropriate 
pins of all processor system bus agents.

DSTBN[3:0]#

Input/

Output

Data strobe used to latch in D[63:0]#.

DSTBP[3:0]#

Input/

Output

Data strobe used to latch in D[63:0]#.

FERR#

Output

FERR# (Floating-point Error) is asserted when the processor detects an unmasked 
floating-point error. FERR# is similar to the ERROR# signal on the Intel 387 
coprocessor, and is included for compatibility with systems using MS-DOS*-type 
floating-point error reporting.

GTLREF

Input

GTLREF determines the signal reference level for AGTL+ input pins. GTLREF 
should be set at 2/3 V

CC

. GTLREF is used by the AGTL+ receivers to determine if a 

signal is a logical 0 or logical 1. Refer to the Intel

 

850 Chipset Platform Design Guide for more information.

HIT#

HITM#

Input/

Output

Input/

Output

HIT# (Snoop Hit) and HITM# (Hit Modified) convey transaction snoop operation 
results. Any system bus agent may assert both HIT# and HITM# together to 
indicate that it requires a snoop stall, which can be continued by reasserting HIT# 
and HITM# together.

IERR#

Output

IERR# (Internal Error) is asserted by a processor as the result of an internal error. 
Assertion of IERR# is usually accompanied by a SHUTDOWN transaction on the 
processor system bus. This transaction may optionally be converted to an external 
error signal (e.g., NMI) by system core logic. The processor will keep IERR# 
asserted until the assertion of RESET#, BINIT#, or INIT#. 

IGNNE#

Input

IGNNE# (Ignore Numeric Error) is asserted to force the processor to ignore a 
numeric error and continue to execute noncontrol floating-point instructions. If 
IGNNE# is deasserted, the processor generates an exception on a noncontrol 
floating-point instruction if a previous floating-point instruction caused an error. 
IGNNE# has no effect when the NE bit in control register 0 (CR0) is set.

IGNNE# is an asynchronous signal. However, to ensure recognition of this signal 
following an Input/Output write instruction, it must be valid along with the TRDY# 
assertion of the corresponding Input/Output Write bus transaction.

D[15:0]#, DBI0# 

DSTBN0#

D[31:16]#, DBI1# 

DSTBN1#

D[47:32]#, DBI2# 

DSTBN2#

D[63:48]#, DBI3# 

DSTBN3#

D[15:0]#, DBI0# 

DSTBP0#

D[31:16]#, DBI1# 

DSTBP1#

D[47:32]#, DBI2# 

DSTBP2#

D[63:48]#, DBI3# 

DSTBP3#