Intel Core 2 Extreme QX6850 BX80569QX6850 User Manual
Product codes
BX80569QX6850
Electrical Specifications
32
Datasheet
2.7.7
Phase Lock Loop (PLL) and Filter
An on-die PLL filter solution will be implemented on the processor. The VCCPLL input is
used for the PLL. Refer to
for DC specifications.
2.7.8
BCLK[1:0] Specifications (CK505 based Platforms)
Table 17.
BSEL[2:0] Frequency Table for BCLK[1:0]
BSEL2
BSEL1
BSEL0
FSB Frequency
L
L
L
266 MHz
L
L
H
RESERVED
L
H
H
RESERVED
L
H
L
200 MHz
H
H
L
RESERVED
H
H
H
RESERVED
H
L
H
RESERVED
H
L
L
333 MHz
Table 18.
Front Side Bus Differential BCLK Specifications
Symbol
Parameter
Min
Typ
Max
Unit Figure Notes
1
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
V
L
Input Low Voltage
-0.30
N/A
N/A
V
2
2. "Steady state" voltage, not including overshoot or undershoot.
V
H
Input High Voltage
N/A
N/A
1.15
V
V
CROSS(abs)
Absolute Crossing Point
0.300
N/A
0.550
V
3, 4, 5
3. Crossing voltage is defined as the instantaneous voltage value when the rising edge of BCLK0
equals the falling edge of BCLK1.
4. V
Havg
is the statistical average of the V
H
measured by the oscilloscope.
5. The crossing point must meet the absolute and relative crossing point specifications
simultaneously.
ΔV
CROSS
Range of Crossing Points
N/A
N/A
0.140
V
V
OS
Overshoot
N/A
N/A
1.4
V
6
6. Overshoot is defined as the absolute value of the maximum voltage. Undershoot is defined as
the absolute value of the minimum voltage.
V
US
Undershoot
-0.300 N/A
N/A
V
V
SWING
Differential Output Swing
0.300
N/A
N/A
V
7
7. Measurement taken from differential waveform.
I
LI
Input Leakage Current
-5
N/A
5
μA
Cpad
Pad Capacitance
.95
1.2
1.45
pF
8
8. Cpad includes die capacitance only. No package parasitics are included.