Intel Core 2 Extreme QX6850 BX80569QX6850 User Manual

77

THERMTRIP#

Output

In the event of a catastrophic cooling failure, the processor will 
automatically shut down when the silicon has reached a 
temperature approximately 20 °C above the maximum T

C

. 

Assertion of THERMTRIP# (Thermal Trip) indicates the processor 
junction temperature has reached a level beyond where permanent 
silicon damage may occur. Upon assertion of THERMTRIP#, the 
processor will shut off its internal clocks (thus, halting program 
execution) in an attempt to reduce the processor junction 
temperature. To protect the processor, its core voltage (V

CC

) must 

be removed following the assertion of THERMTRIP#.  Driving of the 
THERMTRIP# signal is enabled within 10 μs of the assertion of 
PWRGOOD (provided V

TT

 and V

CC

 are valid) and is disabled on de-

assertion of PWRGOOD (if V

TT

 or V

CC

 are not valid, THERMTRIP# 

may also be disabled). Once activated, THERMTRIP# remains 
latched until PWRGOOD, V

TT

, or V

CC

 is de-asserted. While the de-

assertion of the PWRGOOD, V

TT

, or V

CC

 will de-assert THERMTRIP#, 

if the processor’s junction temperature remains at or above the trip 
level, THERMTRIP# will again be asserted within 10 μs of the 
assertion of PWRGOOD (provided V

TT

 and V

CC

 are valid).

TMS

Input

TMS (Test Mode Select) is a JTAG specification support signal used 
by debug tools.

TRDY#

Input

TRDY# (Target Ready) is asserted by the target to indicate that it is 
ready to receive a write or implicit writeback data transfer. TRDY# 
must connect the appropriate pins/lands of all FSB agents.

TRST#

Input

TRST# (Test Reset) resets the Test Access Port (TAP) logic. TRST# 
must be driven low during power on Reset. 

VCC

Input

VCC are the power pins for the processor. The voltage supplied to 
these pins is determined by the VID[7:0] pins.

VCCPLL

Input

VCCPLL provides isolated power for internal processor FSB PLLs.

VCC_SENSE

Output

VCC_SENSE is an isolated low impedance connection to processor 
core power (V

CC

). It can be used to sense or measure voltage near 

the silicon with little noise.

VCC_MB_
REGULATION

Output

This land is provided as a voltage regulator feedback sense point for 
V

CC

. It is connected internally in the processor package to the sense 

point land U27 as described in the Voltage Regulator-Down (VRD) 
11.0 Processor Power Delivery Design Guidelines For Desktop 
LGA775 Socket.

VID[7:0]

Output

VID[7:0] (Voltage ID) signals are used to support automatic 
selection of power supply voltages (V

CC

). Refer to the Voltage 

Regulator-Down (VRD) 11.0 Processor Power Delivery Design 
Guidelines For Desktop LGA775 Socket for more information. The 
voltage supply for these signals must be valid before the VR can 
supply V

CC

 to the processor. Conversely, the VR output must be 

disabled until the voltage supply for the VID signals becomes valid. 
The VID signals are needed to support the processor voltage 
specification variations. See 

 for definitions of these signals. 

The VR must supply the voltage that is requested by the signals, or 
disable itself.

VID_SELECT

Output

This land is tied high on the processor package and is used by the 
VR to choose the proper VID table. Refer to the Voltage Regulator-
Down (VRD) 11.0 Processor Power Delivery Design Guidelines For 
Desktop LGA775 Socket for more information.