Intel Celeron M 2.4GHz RH80532NC056256 User Manual
Product codes
RH80532NC056256
R
Specification Update
31
V44.
Memory Aliasing of Pages as Uncacheable Memory Type and Write Back (WB)
May Hang the System
Problem:
When a page is being accessed as either Uncacheable (UC) or Write Combining (WC) and WB, under
certain bus and memory timing conditions, the system may loop in a continual sequence of UC fetch,
implicit writeback, and Request For Ownership (RFO) retries.
certain bus and memory timing conditions, the system may loop in a continual sequence of UC fetch,
implicit writeback, and Request For Ownership (RFO) retries.
Implication: This erratum has not been observed in any commercially available operating system or application. The
aliasing of memory regions, a condition necessary for this erratum to occur, is documented as being
unsupported in the IA-32 Intel® Architecture Software Developer's Manual, Volume 3, section 10.12.4,
Programming the PAT. However, if this erratum occurs the system may hang.
unsupported in the IA-32 Intel® Architecture Software Developer's Manual, Volume 3, section 10.12.4,
Programming the PAT. However, if this erratum occurs the system may hang.
Workaround: The pages should not be mapped as either UC or WC and WB at the same time.
Status:
For the steppings affected, see the Summary Tables of Changes.
V45.
A Timing Marginality in the Arithmetic Logic Unit (ALU) May Cause Indeterminate
Behavior
Problem: A timing marginality may exist in the clocking of the ALU which leads to a slowdown in the speed of
the circuit’s operation. This could lead to incorrect behavior of the ALU.
Implication: When this erratum occurs, unpredictable application behavior and/or system hang may occur.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status:
For the steppings affected see the Summary Tables of Changes.
V46.
With TF (Trap Flag) Asserted, FP Instruction That Triggers an Unmasked FP
Exception May Take Single Step Trap Before Retirement of Instruction
Exception May Take Single Step Trap Before Retirement of Instruction
Problem: If an FP instruction generates an unmasked exception with the EFLAGS.TF=1, it is possible for external
events to occur, including a transition to a lower power state. When resuming from the lower power
state, it may be possible to take the single step trap before the execution of the original FP instruction
completes.
state, it may be possible to take the single step trap before the execution of the original FP instruction
completes.
Implication: A Single Step trap will be taken when not expected.
Workaround: None identified.
Status:
For the steppings affected see the Summary Tables of Changes.