Intel Xeon X3470 BX80605X3470 User Manual
Product codes
BX80605X3470
Intel® Xeon® Processor 3400 Series Datasheet, Volume 1
5
Electrical Specifications ........................................................................................... 59
7.1
7.1
7.10 Platform Environmental Control Interface (PECI) DC Specifications........................... 74
Processor Land and Signal Information ................................................................... 77
8.1
8.1
Figures
®
Xeon
®
Processor 3400 Series Platform Diagram ................................................. 10
2-1 Intel® Flex Memory Technology Operation .................................................................. 21
2-2 Dual-Channel Symmetric (Interleaved) and Dual-Channel Asymmetric Modes .................. 22
2-3 PCI Express Layering Diagram ................................................................................... 24
2-4 Packet Flow through the Layers ................................................................................. 25
2-5 PCI Express* Related Register Structures in Processor ................................................. 26
4-1 Idle Power Management Breakdown of the Processor Cores ........................................... 35
4-2 Thread and Core C-State Entry and Exit ...................................................................... 36
4-3 Package C-State Entry and Exit.................................................................................. 40
7-1 VCC Static and Transient Tolerance Loadlines ............................................................. 71
7-2 Input Device Hysteresis ............................................................................................ 75
8-1 Socket Pinmap (Top View, Upper-Left Quadrant) .......................................................... 78
8-2 Socket Pinmap (Top View, Upper-Right Quadrant) ........................................................ 79
8-3 Socket Pinmap (Top View, Lower-Left Quadrant) .......................................................... 80
8-4 Socket Pinmap (Top View, Lower-Right Quadrant) ........................................................ 81
2-2 Dual-Channel Symmetric (Interleaved) and Dual-Channel Asymmetric Modes .................. 22
2-3 PCI Express Layering Diagram ................................................................................... 24
2-4 Packet Flow through the Layers ................................................................................. 25
2-5 PCI Express* Related Register Structures in Processor ................................................. 26
4-1 Idle Power Management Breakdown of the Processor Cores ........................................... 35
4-2 Thread and Core C-State Entry and Exit ...................................................................... 36
4-3 Package C-State Entry and Exit.................................................................................. 40
7-1 VCC Static and Transient Tolerance Loadlines ............................................................. 71
7-2 Input Device Hysteresis ............................................................................................ 75
8-1 Socket Pinmap (Top View, Upper-Left Quadrant) .......................................................... 78
8-2 Socket Pinmap (Top View, Upper-Right Quadrant) ........................................................ 79
8-3 Socket Pinmap (Top View, Lower-Left Quadrant) .......................................................... 80
8-4 Socket Pinmap (Top View, Lower-Right Quadrant) ........................................................ 81