Intel Celeron 1.1GHz RK80530RY005256 Data Sheet

122

EDGCTRL

I

The EDGCTRL input provides AGTL+ edge control and should be pulled up to 
V

CCCORE

 with a 51 

Ω

 ± 5% resistor.

NOTE: This signal is NOT used on the FC-PGA/FC-PGA2 packages.

EMI
(S.E.P.P. only)

I

EMI pins should be connected to motherboard ground and/or to chassis ground 
through zero ohm (0

Ω

) resistors. The zero ohm resistors should be placed in close 

proximity to the Intel Celeron processor connector. The path to chassis ground 
should be short in length and have a low impedance. These pins are used for EMI 
management purposes.

FERR# O

The FERR# (Floating-point Error) signal is asserted when the processor detects an 
unmasked floating-point error. FERR# is similar to the ERROR# signal on the 
Intel 387 coprocessor, and is included for compatibility with systems using MS-
DOS*-type floating-point error reporting.

FLUSH#

I

When the FLUSH# input signal is asserted, the processor writes back all data in the 
Modified state from the internal cache and invalidates all internal cache lines. At the 
completion of this operation, the processor issues a Flush Acknowledge transaction. 
The processor does not cache any new data while the FLUSH# signal remains 
asserted.

FLUSH# is an asynchronous signal. However, to ensure recognition of this signal 
following an I/O write instruction, it must be valid along with the TRDY# assertion of 
the corresponding I/O Write bus transaction.

On the active-to-inactive transition of RESET#, the processor samples FLUSH# to 
determine its power-on configuration. See Pentium

®

 (Order Number 242690) for details. 

HIT#, HITM#

I/O

The HIT# (Snoop Hit) and HITM# (Hit Modified) signals convey transaction snoop 
operation results, and must connect the appropriate pins of all Intel Celeron 
processor system bus agents. Any such agent may assert both HIT# and HITM# 
together to indicate that it requires a snoop stall, which can be continued by 
reasserting HIT# and HITM# together.

IERR#

O

The IERR# (Internal Error) signal is asserted by a processor as the result of an 
internal error. Assertion of IERR# is usually accompanied by a SHUTDOWN 
transaction on the Intel Celeron processor system bus. This transaction may 
optionally be converted to an external error signal (e.g., NMI) by system core logic. 
The processor will keep IERR# asserted until the assertion of RESET#, BINIT#, or 
INIT#.

IGNNE#

I

The IGNNE# (Ignore Numeric Error) signal is asserted to force the processor to 
ignore a numeric error and continue to execute noncontrol floating-point instructions. 
If IGNNE# is deasserted, the processor generates an exception on a noncontrol 
floating-point instruction if a previous floating-point instruction caused an error. 
IGNNE# has no effect when the NE bit in control register 0 is set.

IGNNE# is an asynchronous signal. However, to ensure recognition of this signal 
following an I/O write instruction, it must be valid along with the TRDY# assertion of 
the corresponding I/O Write bus transaction.

INIT#

I

The INIT# (Initialization) signal, when asserted, resets integer registers inside all 
processors without affecting their internal (L1) caches or floating-point registers. 
Each processor then begins execution at the power-on Reset vector configured 
during power-on configuration. The processor continues to handle snoop requests 
during INIT# assertion. INIT# is an asynchronous signal and must connect the 
appropriate pins of all bus agents.

If INIT# is sampled active on the active to inactive transition of RESET#, then the 
processor executes its Built-in Self-Test (BIST).