Intel Xeon E5530 P4X-DPE5530-240-8M586 User Manual

Intel

®

 Xeon

®

 Processor 5500 Series Datasheet, Volume 1

105

The processor uses Frequency/VID control whereby TCC activation causes the 

processor to adjust its operating frequency (via the core ratio multiplier) and input 

voltage (via the VID signals). This combination of reduced frequency and VID results in 

a reduction to the processor power consumption.

This method includes multiple operating points, each consisting of a specific operating 

frequency and voltage. The first operating point represents the normal operating 

condition for the processor. The remaining points consist of both lower operating 

frequencies and voltages. When the TCC is activated, the processor automatically 

transitions to the new operating frequency. This transition occurs very rapidly (on the 

order of 2 µs).

Once the new operating frequency is engaged, the processor will transition to the new 

core operating voltage by issuing a new VID code to the voltage regulator. The voltage 

regulator must support dynamic VID steps to support this method. During the voltage 

change, it will be necessary to transition through multiple VID codes to reach the target 

operating voltage. Each step will be one VID table entry (see 

). The processor 

continues to execute instructions during the voltage transition. Operation at the lower 

voltages reduces the power consumption of the processor.

A small amount of hysteresis has been included to prevent rapid active/inactive 

transitions of the TCC when the processor temperature is near its maximum operating 

temperature. Once the temperature has dropped below the maximum operating 

temperature, and the hysteresis timer has expired, the operating frequency and 

voltage transition back to the normal system operating point via the intermediate 

VID/frequency points. Transition of the VID code will occur first, to insure proper 

operation once the processor reaches its normal operating frequency. Refer to 

 for an illustration of this ordering.

f

MAX

f

1

f

2

VIDf

MAX

VIDf

2

VIDf

1

f

MAX

f

1

f

2

VIDf

MAX

VIDf

2

VIDf

1