Intel Xeon E5530 P4X-DPE5530-240-8M586 User Manual
Product codes
P4X-DPE5530-240-8M586
Intel
®
Xeon
®
Processor 5500 Series Datasheet, Volume 1
39
Intel® Xeon® Processors 5500 Series Electrical Specifications
Notes:
1.
The V
TT_MIN
and V
TT_MAX
loadlines represent static and transient limits. Each is characterized by a ±31.5 mV
offset from V
TT_TYP
.
2.
Refer to
for processor VTT_VID information.
3.
Refer to
for V
TT
Static and Transient Tolerance.
Figure 2-10. V
TT
Static and Transient Tolerance Loadlines
-0.2125
-0.2000
-0.1875
-0.1750
-0.1625
-0.1500
-0.1375
-0.1250
-0.1125
-0.1000
-0.0875
-0.0750
-0.0625
-0.0500
-0.0375
-0.0250
-0.0125
0.0000
0.0125
0.0250
0.0375
0.0500
0
5
10
15
20
25
I
TT
[A]
VT
T_
VID DevIatIo
n
Table 2-12. DDR3 Signal Group DC Specifications (Sheet 1 of 2)
Symbol
Parameter
Min
Typ
Max
Units
Notes
1
V
IL
Input Low Voltage
0.43*V
DDQ
V
2,
V
IH
Input High Voltage
0.57*V
DDQ
V
3, 4
V
OL
Output Low Voltage
(V
DDQ
/ 2)* (R
ON
/(R
ON
+R
VTT_TERM
))
V
6
V
OH
Output High Voltage
V
DDQ
- ((V
DDQ
/ 2)*
(R
ON
/(R
ON
+R
VTT_TERM
))
V
4,6
R
ON
DDR3 Clock Buffer On
Resistance
21
31
Ω
5
R
ON
DDR3 Command Buffer
On Resistance
16
24
Ω
5
R
ON
DDR3 Reset Buffer On
Resistance
25
75
Ω
5
R
ON
DDR3 Control Buffer
On Resistance
21
31
Ω
5
R
ON
DDR3 Data Buffer On
Resistance
21
31
Ω
5
Data ODT
On-Die Termination for
Data Signals
45
90
90
55
110
Ω
7
ParErr ODT On-Die Termination for
Parity Error bits
60
80
Ω