Intel E5504 AT80602000801AA User Manual

136

Intel

®

 Xeon

®

 Processor 5500 Series Datasheet, Volume 1

The processor supports the ACPI sleep states S0, S1, S3, and S4/S5 as shown in. For 
information on ACPI S-states and related terminology, refer to ACPI Specification. The 
S-state transitions are coordinated by the processor in response PM Request (PMReq) 
messages from the chipset. The processor itself will never request a particular S-state.

1.

If the chipset requests an S-state transition which is not allowed, a machine check error 
will be generated by the processor.

The processor supports ACPI Performance States (P-States). The P-state referred to as 
P0 will be a request for Intel

®

 Turbo Boost Technology (Intel

®

 TBT). Intel TBT 

opportunistically, and automatically, allows the processor to run faster than the marked 
frequency if the part is operating below power, temperature and current limits. Max 
Turbo Boost frequency is dependent on the number of active cores and varies by 
processor line item configuration. Intel TBT doesn’t need special hardware support, and 
can be enabled or disabled by BIOS.

The processor features Enhanced Intel SpeedStep

®

 Technology. Following are the key 

features of Enhanced Intel SpeedStep Technology:

• Multiple voltage and frequency operating points provide optimal performance at the 

lowest power. 

• Voltage and frequency selection is software controlled by writing to processor 

MSRs:

— If the target frequency is higher than the current frequency, V

CC

 is ramped up 

in steps by placing new values on the VID pins and the PLL then locks to the 

new frequency.

— If the target frequency is lower than the current frequency, the PLL locks to the 

new frequency and the V

CC

 is changed through the VID pin mechanism.

— Software transitions are accepted at any time. If a previous transition is in 

progress, the new transition is deferred until the previous transition completes.

• The processor controls voltage ramp rates internally to ensure smooth transitions.
• Low transition latency and large number of transitions possible per second:

— Processor core (including shared cache) is unavailable for less than 2µs during 

the frequency transition.

S0

Normal Code Execution

S1 (via PMReq)

S1

Cores in C1E like state, processor responds with 

CmpD(S1) message.

S0 (via reset or PMReq)
S3, S4 (via PMReq)

S3

Memory put into self-refresh, processor responds with 

CmpD(S3) message.

S0 (via reset)

S4/S5

Processor responds with CmpD(S4/S5) message.

S0 (via reset)